JPH0454070A - Binarizing circuit - Google Patents

Abstract

PURPOSE:To realize a binarizing circuit coping with plural data forms by selecting a comparator level to read a data storage means in response to a data form and making the arithmetic processing available independently of the data form. CONSTITUTION:The method of generating an address 9 is changed in response to data arrangement of each color and the address is outputted to a ROM 2 by allowing a control circuit 1 to receive a data form signal 6 representing whether a form of an input picture data is a point sequential data, a line sequential data or an area sequential data, a line signal 5 representing a valid range of a data, and a clock 8 synchronously with an input data. A comparator 3 is equivalent to a comparison means and uses an 8-bit output from the ROM 2 as a comparator level to binarize an 8-bit input data 7.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a binarization circuit used in image devices such as image scanners, printers, and copiers, and in particular to a binarization circuit used in image devices such as image scanners, printers, and copiers, and in particular to a binary conversion circuit that handles color image data. Regarding the value conversion circuit.

[Conventional technology]

2. Description of the Related Art Conventionally, in image processing apparatuses that handle two-dimensional color image data, image scanners often use line sequential data, and printers and copying machines often use field sequential data. For example, R (red), G
For example, input data separated into three primary colors (green) and B (blue) is shown in Figure 30 for point sequential data, Figure 31 for line sequential data, and Figure 32 for field sequential data. In the main scanning direction, every second pixel is the same color for dot sequential data, all pixels are the same color for line sequential data and field sequential data, and in the sub scanning direction, every two pixels are the same color for dot sequential data and field sequential data. The whole line is
In line sequential data, the same color data is provided every two lines.

On the other hand, in imaging equipment, two-dimensional
Although digitizing circuits are often used, the data arrangement differs depending on the data format, and therefore a specific binarizing circuit is configured depending on each data format.

[Problems to be Solved by the Invention] In the conventional technology as described above, the binarization circuit lacks versatility, and it is difficult to connect it to other devices with different data formats. For example, the binarization circuit used in image scanners that often use vA 1-head data as a data format cannot be used in printers and copiers that often use frame-sequential data; I had to prepare a circuit.

Therefore, it is an object of the present invention to provide a binarization circuit that can handle a plurality of data formats.

[Means to solve the problem]

In order to solve the above problems, in the present invention, in a binarization circuit that performs 2(+!! conversion processing) on color image data, a comparator level corresponding to each pixel and used for the binarization processing is set. A data storage means for storing data, a control means for controlling an address value to be supplied to the data storage means according to the data format, and a comparison level of the address value designated by the control means to input pixel data. It is characterized by comprising a comparison means that performs value conversion processing and outputs it.

[Effect]

According to the above configuration, the comparator level to be read from the data storage means is selected based on the data format based on the control means, and arithmetic processing can be performed regardless of the data format.

〔Example〕

FIG. 1 is a structural block diagram of an embodiment of the present invention, and is a structural block diagram of a dither circuit for creating halftones.

The control means 1 is for eliminating the influence on calculations due to the difference in data arrangement between each data format, for example, the use of data of a different color when calculating data of the same color. It is composed of a counter, etc., and is synchronized with the input data with a data format signal 6 indicating whether the format of the input image data is dot sequential data, line sequential data, or plane sequential data, and a line signal 5 indicating the effective range of the data. By inputting the clock 8, the generation method of the address 9 is changed according to the data arrangement of each color and outputted to the ROM 2. As shown in FIG. 2, the control means 1 is configured to output the upper 2 bits and lower 2 bits of the address.
The part that outputs the upper two bits has a line counter 10 that counts three lines, an A input, and a B input, and outputs either the A input or B input signal based on the signal input to the select terminal. It consists of a selector 11 and an upper address counter 12 that counts addresses in synchronization with a clock, and the counter input of the line counter 10 and the selector 11
The line signal 5 is input to the enable terminal of the upper address counter 12, and the B input of the selector 11
The Q output of the line counter 10 is input to the input, and the data format signal 6 is input to the select terminal. A selector 11 is connected to the reset terminal of the upper address counter.
The Y output of 8 is connected, and the clock 8 is connected to the clock terminal.
has been entered. The part that outputs the lower 2 bits is a clock counter 20 that counts 3 clocks, 6 inputs, B
a selector 21 that has an input and outputs either 6-input or 8-input signals based on the signal input to the select terminal;
, and a lower address counter 22 that counts addresses in synchronization with a clock.The line signal 5 is input to the counter input of the clock counter 20, the A input of the selector 21, and the enable terminal of the lower address counter 22. The Q output of the clock counter 20 is input to the B input of 21, and the data format signal 6 is input to the select terminal.

The Y output 24 of the selector 21 is connected to the reset terminal of the lower address counter, and the clock 8 is input to the clock terminal. 2 by data format signal 6
The reset signals 1-4.24 of the 2-bit upper address counter 12 and the 2-bit lower address counter 22 are selected. Reset signal 14 for upper address counter 12
is 5 line signals, or 1 line signal for 3 lines.
The reset signal 24 of the lower address counter 22 is the clock 8.
or a 3-clock signal 71 in which 1 clock is 3 clocks. As a result, the control means 1 outputs address 9 to the ROM 2 in accordance with the data format.

The ROM 2 corresponds to a data storage means and stores a dither pattern. For example, the 4×4 dither pattern shown in FIG. 3 is stored in accordance with the address map shown in FIG. 4.

The comparator 3 corresponds to comparison means, and uses the 8-bit output of the ROM 2 as a comparison level, and binarizes the 8-bit input data 7.

Next, the operation shown in FIG. 1 will be explained.

In the case of point sequential data, the selector 11 selects the line signal 5 and the selector 21 selects the 3-clock signal 23 according to the data format signal 6, and as shown in FIG. Output the rate level.

In the case of line sequential data, the selector 11 selects the 3-line signal 13 and the selector 67 selects the clock signal 8 according to the data format signal 6, and as shown in FIG. Output the rate level.

In the case of frame sequential data, the selector 11 outputs the line signal 5 according to the data format signal 6, and the selector 21 outputs the clock signal 8.
is selected, address 9 is generated every four lines as shown in FIG. 27, and a comparator level is output from ROM2.

Using the comparison level obtained above, the human data 7 is binarized and output.

〔Effect of the invention〕

As explained above, the present invention enables arithmetic processing for each data format, significantly improves the versatility of the binarization circuit, and facilitates connection with other devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of an embodiment of the present invention, FIG. 2 is a block diagram of the control means 1, and FIG. 3 is a dither pattern used in the dither circuit of the embodiment of the present invention. The figure is R
In the address map of OM2, FIG. 5 is a timing chart during point-sequential data processing in the dither circuit according to the embodiment of the present invention, and FIG. 6 is a timing chart during line-sequential data processing in the dither circuit according to the embodiment of the present invention. FIG. 7 is a timing chart during field-sequential pig processing in the dither circuit according to the embodiment of the present invention, FIG. 8 is an explanatory diagram showing the data arrangement of point-sequential data, and FIG. 9 is a diagram showing the data arrangement of line-sequential data. FIG. 10 is an explanatory diagram showing the data arrangement of the frame sequential data. 1... Control circuit 2 ・ ・ ・ ROM 3... Comparator and above Applicant Seiko Electronics Co., Ltd. Agent Patent attorney Takayuki Hayashi
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Claims (1)

[Scope of Claim] A binarization circuit that performs binarization processing on color image data, comprising: a data storage means for storing a comparator level corresponding to each pixel and used in the binarization processing; comprising a control means for controlling an address value supplied to the data storage means, and a comparison means for performing binarization processing on the input pixel data and outputting the result using a comparison level of the address value specified by the control means. An image processing device characterized by: