JPH0454319B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a semiconductor memory device having a memory cell array in which a plurality of memory cells are arranged in rows and columns and a plurality of I/O data lines, and particularly to a redundant circuit thereof. .

Conventional technology The integration density of semiconductor memory has significantly improved, and dynamic random access memory (DRAM)
In today's world, devices with a capacity of 1M bits are becoming mainstream. Such large capacity random
Access memories generally include redundant circuits to reduce manufacturing costs. This system has spare memory cells in addition to the regular memory cells on the memory chip, and if a defect is found in some of the regular memory cells during wafer inspection, this is replaced with the spare memory cell, and a small number of defective bits are removed from the chip. The aim is to provide relief to Specifically, in a memory cell array in which a plurality of memory cells are arranged in rows and columns, a spare row or a spare column, or both, are provided to replace a row or column containing a defective memory cell, and the defective memory cell is When a row address or a column address of a row or column containing the memory cell array is selected, the row or column in the regular memory cell array is not selected, but a spare row or column is selected.

Another trend accompanying the increase in the degree of integration of semiconductor memories is the diversification of bit configurations. Conventionally,
Since DRAM was often used in large quantities as the main memory of computers, a x1-bit configuration that accessed one memory cell at a time was sufficient. However, as the cost per bit has declined, the field of DRAM applications has expanded;
As the number of memory cells that can be integrated on a chip has become extremely large, a multi-bit configuration that accesses several memory cells simultaneously is now available.
Demand for DRAM is also increasing. As a multi-bit configuration memory, DRAM currently has ×4
Many static random access memories (SRAMs) have an x8-bit configuration, but in the future, memories with x16-bit, x32-bit, and even x64-bit configurations will be needed. It is expected that it will get older.

An example in which a conventional redundant circuit is applied to such a multi-bit memory device is shown in FIGS. 5 and 6. In FIGS. 5 and 6, in order to simplify the explanation, a ×4 bit configuration and a case where the number of column addresses is 4 are illustrated. Also, column lines and I/
In reality, two O data lines, including a line for complementary data, form a pair in most cases, but this is also represented by one line for simplicity.

FIG. 5 shows an example in which bit lines (column lines) having a common column address are arranged adjacent to each other. The bit lines B ₁ , B ₂ , . . . , B ₁₆ are regular bit lines. D ₁ , D ₂ , D ₃ , and D ₄ are I/O data lines corresponding to each of the 4 bits of input/output data. Transistors T ₁ , T ₂ , ..., T ₁₆ are regular column decoders 1
According to the column selection signal lines C ₁ , C ₂ , C ₃ , and C ₄ that are decoded and activated by 0, the regular bit lines are activated.
B ₁ to B ₁₆ and I/O data lines D ₁ to _{D 4} are electrically connected. B ₁₇ , B ₁₈ , B ₁₉ , and B ₂₀ are spare bit lines, and memory cells on any of the regular bit lines B ₁ to _{B 16} electrically connected to the I/O data lines D ₁ to _{D 4} If there is a defect in the original bit line,
Replace B ₁ to _{B 16} with spare bit lines B ₁₇ to _{B 20} . Redundant column decoder 20 activates redundant column selection signal line _C5 when a column address including a defective memory cell is selected. As a result, transistors T ₁₇ , T ₁₈ , T ₁₉ , and T ₂₀ become conductive, and spare bit lines B ₁₇ to _{B 20} are electrically connected to I/O data lines D ₁ to _{D 4} . At the same time, the column selection signal line, which would be activated at this column address if there is no defect in the normal memory cell, remains inactive.
The column address for activating the redundant column selection signal line is set by cutting a portion of the fuse previously formed on the chip with a laser after a defective memory cell is discovered during wafer inspection.

FIG. 6 shows an example in which bit lines electrically connected to the same I/O data line are arranged adjacent to each other. As shown in FIG. 6, the regular bit lines B ₁ , B ₂ ,
..., _B16 are divided into four blocks and arranged for each corresponding I/O data line. In this case, column decoders 10, 11, 12, and 13 are arranged for each block, and column selection signal lines are selected according to the column address.
C ₀₁ , C ₀₂ , C ₀₃ , C ₀₄ , C ₁₁ , C ₁₂ , C ₁₃ , C ₁₄ , C ₂₁ ,
One from each block among C ₂₂ , C ₂₃ , C ₂₄ , C ₃₁ , C ₃₂ , C ₃₃ , and C ₃₄ , for example, column selection signal line C ₀₁ ,
Activates C ₁₁ , C ₂₁ , and C ₃₁ . Spare bit line B ₁₇ ,
B ₁₈ , B ₁₉ , B ₂₀ , redundant column decoders 20, 21, 2
2 and 23 are also arranged one each for each block. When a column address belonging to a defective memory cell is selected, the redundant column selection signal line C ₀₅ ,
C ₁₅ , C ₂₅ , and C ₃₅ are all activated, and the transistor
T ₁₇ , T ₁₈ , T ₁₉ , T ₂₀ are conductive and the spare bit line
B ₁₇ , B ₁₈ , B ₁₉ , B ₂₀ are I/O data lines respectively
Electrically connected to D ₁ , D ₂ , D ₃ , and D ₄ . at the same time,
In each column decoder 10-13, the column selection signal line, which would be activated at this column address if no normal memory cell is defective, remains inactive.

Problems to be Solved by the Invention Incidentally, the situation in which defective memory cells occur is not completely random, but may occur when adjacent memory cells become defective at the same time, or when adjacent bit lines are short-circuited and two columns are It is often seen that both become defective at the same time. However, in the column redundancy circuit shown in Figure 6, only one bit line in each block is replaced with a redundant bit line, so if vertically adjacent memory cells become defective at the same time or if adjacent bit lines If a fault occurs due to a short circuit between lines, it is impossible to repair the problem. Therefore, in the case of FIG. 6, there is a drawback that the defect recovery rate by the redundant circuit is not very high.

On the other hand, the case of FIG. 5 has the advantage that even if a defective memory cell exists across two or more columns, it can be replaced with a spare bit line as long as it is within the same column address range. . However, in the case of FIG. 5, the transfer gate transistors T ₁ , T ₂ , . . . , which electrically connect the bit line and the I/O data line
Since T ₂₀ is placed in the I/O data line wiring area overlapping with I/O data lines D ₁ to _{D 4} , this becomes a layout constraint and the chip area is larger than in the case of Figure 6. Become. Each transistor is
T ₁ , T ₂ , ..., T ₂₀ drains and I/O data lines
It is also possible to connect D ₁ to _{D 4} with wiring that crosses I/O data lines D ₁ to _{D 4} , but in the case of Figure 5, one crossing wiring would be provided for each bit line. 1 for each block.
Compared to the case shown in Figure 6, which only requires cross wiring, I/
The wiring capacitance of the O data lines D ₁ to _{D 4} increases significantly, resulting in a significant decrease in operating speed. Such problems such as an increase in chip area or a decrease in operating speed become more serious as the number of input/output data bits increases.

The present invention provides a semiconductor memory device that solves these conventional problems.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention uses the same circuit and arrangement as the case of FIG. Instead of replacing a bit line with a spare bit line, a redundant circuit is configured to replace a bit line that should be electrically connected to a specific I/O data line with a spare bit line. That is, if a column has a defect, all bit lines that share the I/O data line with that column's bit line are disconnected from that I/O data line, regardless of the column address, and replaced with A group of spare bit lines provided corresponding to each column address and selected according to the column address are connected to the I/O
It electrically connects to the data line.

Effect According to the above configuration, the bit line is connected to the corresponding I/
All defective memory cells are placed together for each O data line, and even if there is a defect across two or more adjacent columns, as long as they are within the same I/O data line block, all defective memory cells are placed in the spare column. It becomes possible to replace it with a memory cell. Therefore, a redundant circuit with high defect relief efficiency can be realized while minimizing the increase in chip area and the decrease in operating speed caused by the increase in the number of bits in the memory configuration.

Embodiment First multi-bit configuration semiconductor memory according to the present invention
An example of this is shown in FIG. In Fig. 1, as in Figs. 5 and 6, in order to simplify the explanation,
The diagram shows a case where the number of column addresses is 4 in a ×4 bit configuration. In FIG. 1, the bit line B ₁ ,
B ₂ , ..., B ₁₆ are 4 for each corresponding I/O data line.
The bit lines are arranged separately into two blocks, and each block has four bit lines corresponding to each of the four column addresses. Each bit line B ₁ to _{B 16}
As shown in Figure 1, the regular memory cell M ₁
~M ₁₁₆ is connected.

Therefore, when a certain column address is selected,
Column decoders 10, 1 provided for each block
Column selection signal lines C ₀₁ , C ₀₂ ,
C ₀₃ , C ₀₄ ; C ₁₁ , C ₁₂ , C ₁₃ , C ₁₄ ; C ₂₁ , C ₂₂ , C ₂₃ ,
C ₂₄ ; One from each block among C ₃₁ , C ₃₂ , C ₃₃ , C ₃₄ , for example, column selection signal lines C ₀₁ , C ₁₁ , C ₂₁ ,
_C31 is selected and activated. Then, among _the transfer _gate transistors _{T 1} , T _{2 , .} line
B ₁ , ₅ , B ₉ , B ₁₃ are electrically connected to intra-block I/O data lines 30 , 31 , 32 , 33 provided for each block. Intra-block I/O data lines 30, 31, 32, and 33 are connected to fuses F _{30 and 33} , respectively.
I/O data lines _{D 1 , D 2 ,}
Electrically connected to D ₃ and D ₄ .

B ₁₇ , B ₁₈ , B ₁₉ , B ₂₀ are spare bit lines,
4 as well as 1 block of regular bit lines B ₁ to B ₁₆
There are four in total, one for each address. Each spare bit line _B17 to _B20 has a first
As shown in the figure, spare memory cells M ₁₇ to M ₁₂₀ are connected. The block of spare bit lines B ₁₇ to _{B 20} also includes a column decoder 14, and when a certain column address is selected, the column selection signal lines C ₄₁ , C ₄₂ , C ₄₃ , C ₄₄
One of them, for example, column selection signal line _C41 , is selected and activated. Then, among the transfer gate transistors T ₁₇ , T ₁₈ , T ₁₉ , and T ₂₀ , the column selection signal line C ₄₁
The transistor _T17 whose gate is connected becomes conductive, and the spare bit line _B17 and the intra-block I/O data line 34 of the spare bit line block are electrically connected.

If a defective memory cell (eg, M ₁ , M ₁₀₁ ) electrically connected to bit line B ₁ is found to be defective on a normal bit line, then the I/O data line D ₁ and the intrablock I/O The fuse F ₃₀ connecting with the O data line 30 is cut by laser beam irradiation. By doing this, the I/O data line D ₁ has regular memory cells (for example, M ₁ , M ₁₀₁ ).
is no longer electrically connected. Then, instead of cutting fuse _F1 , transfer gate transistor
Among T ₂₁ , T ₂₂ , T ₂₃ , and T ₂₄ , the transistor T ₂₁ between the I/O data line D ₁ and the I/O data line 34 in the spare block is made conductive, and the other transistors T ₂₂ , Leave T ₂₄ non-conducting.
In this way, the block of bit lines B ₁ , B ₂ , B ₃ , and B ₄ including bit line B ₁ with the defective memory cell is replaced by the spare bit lines B ₁₇ , B ₁₈ , B ₁₉ , and B _{20 .} This means that the memory chip has been replaced with a block, and the memory chip will now operate normally as a whole.
Transistors T ₂₁ , T ₂₂ , T 23 , and T ₂₄ selectively electrically connect between the I/O data line 34 in the spare block and the I/O data lines D ₁ , D ₂ , D ₃ , and _{D 4 .} Gate potentials E ₁ , E ₂ , E ₃ , and E ₄ are normally maintained at ground level by fuses F ₁ to F ₄ , respectively, and transistors T ₂₁ , T ₂₂ , T ₂₃ , and T ₂₄ are in a non-conducting state. It is becoming. However, if the fuse F ₁ between the gate of the transistor T ₂₁ and the ground is cut off, when the transistor T ₂₅ is turned on by the precharge signal PC during the precharge period of the memory, the gate potential E ₁ of the transistor T ₂₁ will change to the power supply. Since it is precharged to a voltage level and then maintains this voltage level, the transistor _T21 is always conductive. As a result, the spare bit line
B ₁₇ , B ₁₈ , B ₁₉ , ₂₀ are column address and therefore column select transfer gate transistors T ₁₇ , T ₁₈ , respectively
T ₁₉ , T ₂₀ , and the bit lines B ₁ , B 2 , _B , which are electrically connected to the I/O data line D ₁ through the transfer gate transistor T ₂₁ controlled by the fuse F ₁ and containing the defective memory cell. ₃ , _B4 will be replaced.

In the above explanation, it was assumed that there is a defect in the memory cell electrically connected to bit line _B1 .
If there is a defective memory cell in B ₂ , B ₃ or B ₄ ,
Alternatively, even if two or more of these wires are defective, the defective bit line can be replaced with a spare bit line by cutting one of the fuses _F1 to _F4 in exactly the same way. You can get memory chips that work normally. More generally, if there is any defect in the normal bit lines B ₁ , B ₂ , ..., B ₁₆ , if it is limited to one block, the appropriate two fuses should be cut. By doing so, defects can be repaired.

As is clear from the above explanation, the first aspect of the present invention
According to this embodiment, the memory cell array of a multi-bit semiconductor memory device is arranged in blocks for each bit of input/output data, which is advantageous in terms of layout, while also preventing defects that span multiple columns, which occur frequently. It is possible to obtain a redundant circuit with high relief efficiency, which can also relieve. Even in the conventional method of replacing the bit line of a specific column address, relief efficiency can be increased if a plurality of column addresses can be replaced with spare bit lines for each block. However, since a plurality of spare bit lines must be provided for each block, the chip area becomes large and the manufacturing cost ends up increasing.
In particular, when the number of input/output data bit lines is equal to or greater than the number of column addresses, using the redundant circuit of the present invention will reduce the chip area, increase the number of defects and reduce the manufacturing cost. significantly lower.

In the embodiment shown in FIG. 1, fuses _F1 to _F4 are connected between the gate electrodes of transfer gate transistors _T21 to _T4 and the ground, respectively.
When one of the fuses is blown, the power supply voltage is applied to the gate electrode of the transistor corresponding to that fuse.
Vcc is applied, the transistor becomes conductive, and the bit line and data line are connected.

However, with this configuration, the gate potential of the transistor in a conductive state becomes a floating state, making it susceptible to noise.

FIG. 2 shows a second embodiment of the present invention that can solve this problem.

In FIG. 2, parts that are the same as those in FIG. 1 are given the same reference numerals and explanations will be omitted, and the explanation will focus on parts that are different from those in FIG. 1.

In FIG. 2, a voltage generating circuit composed of transistors T ₂₉ and T ₃₀ generates a voltage slightly higher than the threshold voltage of the transistors. Since this voltage is applied to the gate electrodes of transistors _T25 to _T28 , transistors _T25 to _T28 have high resistance values. Inverters _I1 to _I4 are connected between the drain electrodes of each transistor _T25 to _T28 and each transfer gate transistor _T21 to _T24 . Hughes F ₁
~ _F4 is drawn between the drain electrode of each transistor _T25 ~ _T28 and the power supply voltage Vcc.

Next, the operation shown in FIG. 2 will be explained.

When normal memory cells M ₁ to _{M 116} are free of defects, all fuses F ₁ to F ₅ are connected.
Therefore, the potential on the input side of inverters _I1 to _I4 in FIG. 2 is approximately equal to the power supply voltage Vcc. Therefore, the gate potentials E ₁ to _{E 4} of the transistors T ₂₁ to T ₂₄ are at the ground potential, and the transistors T ₂₁ to _{T 24} are rendered non-conductive, so that the redundant circuit does not work.

On the other hand, if there is a defect in any of the regular memory cells M ₁ to _{M 116} , for example, if the memory cells M ₁ and M ₁₀₁ connected to the bit line B ₁ are defective, as shown in FIG. Cut fuse _F1 .

When fuse F ₁ is cut, the potential on the input side of inverter I ₁ becomes ground level, and inverter I ₁
The output potential becomes approximately the power supply voltage Vcc, and the transfer gate transistor _T21 becomes conductive. Therefore, bit line B ₁ with defective memory cells M ₁ and M ₁₀₁
This means that the block of bit lines B ₁ , B ₂ , B ₃ , and B ₄ including the bit lines B 1 , B 2 , B 3 , and B 4 has been replaced with the block of spare bit lines B ₁₇ , B ₁₈ , B ₁₉ , and B ₂₀ , and this memory device as a whole is normal. It will work.

Thus, according to the second embodiment of the invention:
When the fuses F ₁ -F ₄ are cut, the gate electrodes of the corresponding transfer gate transistors T ₂₁ -T ₂₄ are connected to ground via the inverters I ₁ -I ₄ and the transistors T ₂₅ -T ₂₈ . In other words, the gate potentials of the transfer gate transistors T ₂₁ to _{T 24} are fixed at a constant high level potential. For this reason, the first
Unlike the embodiment shown in the figure, the gate potential does not go into a floating state, so stable operation that is less susceptible to noise can be expected.

By the way, in the embodiment shown in FIG.
0 to 14, the configuration is shown in which the bit line connected to the left side of each column decoder is selected, but in an actual memory device, the column decoder 1 shown in FIG.
The same bit lines and memory cells shown on the left side of column decoders 10-14 may also be symmetrically connected to the right side of column decoders 10-14. In such a memory device, a fuse is provided corresponding to each column decoder, as shown in the embodiment of FIG.
If F ₃₀ , F ₃₁ , F ₃₂ , and F ₃₃ are connected, fuses must be provided on both the left and right sides of each column decoder, which increases the number of fuses.
Furthermore, in the configuration of FIG. 1, since the fuses F ₃₀ -F ₃₃ are connected to the I/O data lines 30 - 33, the electrical characteristics of the memory device are likely to be influenced by the fuses F ₃₀ -F ₃₃ .

FIG. 3 shows a third embodiment of the present invention that solves this problem. FIG. 3 shows the internal configuration of one column decoder (here, the second column decoder 20).

In FIG. 3, transistors T ₁₀₁ to _{T 116} constitute a column decoding circuit. Each column selection signal line
C ₀₁ to C ₀₄ are connected to ground via transistors T ₁₁₇ to T ₁₂₀ . Transistor T ₁₂₂ , T ₁₂₃
A voltage generation circuit consisting of the following generates a voltage slightly higher than the threshold voltage of the transistor.
Since this voltage is applied to the gate electrode of transistor T ₁₂₁ , transistor T ₁₂₁ has a high resistance value. A fuse _F5 is connected between the column decode circuit and transistor _T121 and the power supply voltage Vcc. The drain potential of transistor T ₁₂₁ is applied to the gate electrodes of transistors T ₁₁₇ to _{T 120} via inverter I ₅ .

Next, the operation shown in FIG. 3 will be explained.

Fuse _F5 is connected when there are no defects in the regular memory cells. Therefore, the potential on the input side of the inverter _I5 is approximately equal to the power supply voltage Vcc, and the output potential of the inverter _I5 becomes the ground level. Therefore, transistors T ₁₁₇ to _{T 120} are all non-conductive.

On the other hand, if a normal memory cell is defective, fuse _F5 is cut. Then, the input side potential of inverter _I5 becomes approximately the ground level, and the output potential of inverter _I5 becomes approximately the power supply voltage. Therefore, all transistors T ₁₁₇ to T ₁₂₀ become conductive, and all column selection signal lines C ₀₁ to _{C 04} become ground level all at once, regardless of the column address where the defective memory cell exists. As a result, bit lines B ₁ to _{B 4} corresponding to column decoder 20 and I/
All transfer gate transistors T ₁ to _{T 4} for connecting the O data line D ₁ become non-conductive.

Thus, according to the embodiment of FIG.
_F5 is connected between the column decode circuit and the power supply and is not connected to the I/O data line. Therefore, the electrical characteristics of the memory device are not adversely affected by the fuse _F5 .

Also, on the right side of Fig. 3, a column decoding circuit, etc., which is symmetrical to the circuit in Fig. 3, is connected, and further on the right side, a first
When symmetrical circuits are connected to the memory cells, bit lines, and column selection signal lines shown in the figure, and a single column decoder is configured to select both left and right bit lines, a common Just by installing one fuse _F5 , both left and right bit lines can be disconnected at once.

By the way, as a special memory device for image processing, it has two types of column addresses, and when multiple data bits are input using one column address,
It is contemplated that the other column address would function to specify each bit of the data. In such a memory device, if a conventional method is implemented with respect to the first column address, that is, a column redundancy circuit that replaces a column with a specific column address with a spare column, the spare column will be replaced with all addresses with respect to the second column address. Therefore, it has been impossible with conventional methods to realize a column redundancy circuit that functions effectively for both column addresses.

FIG. 4 shows a fourth embodiment of the present invention that solves this problem.

FIG. 4 shows the conventional redundant circuit shown in FIG.
This is a combination of the redundant circuits of the first embodiment shown in FIG.

The first column address is input to the first column decoder 15. For these first column addresses, a redundant column decoder 16 is used to implement a redundant circuit. This is the same as the conventional redundant circuit shown in FIG. On the other hand, the second column address is input to second column decoders 10, 11, 12, and 13. For these second column addresses, the circuit shown at the top of FIG. 4, ie, the same redundant circuit as the embodiment of FIG. 1, is added.

Thus, according to the embodiment of FIG. 4, it is possible to add a redundant circuit to a special memory device having two types of column addresses.

Note that the redundant circuit portion of the embodiment shown in FIG. 4 may be replaced with the redundant circuit shown in the embodiment shown in FIG.
Further, the second column decoders 10 to 1 in the embodiment of FIG.
It goes without saying that the interior of the device 4 may be configured as in the embodiment shown in FIG.

Furthermore, in all of the above embodiments, the transfer gate transistors and the like are enhancement type transistors, but they can also be implemented with depression type transistors.

Effects of the Invention According to the present invention, when there is a defective memory cell column in a memory cell array, all bit lines that share an I/O data line with the bit line of that column are removed regardless of the column address. All bit lines are separated from the I/O data line, and instead a group of spare bit lines, which are provided corresponding to each column address and selected according to the column address, are electrically connected to the I/O data line. It is.

In this way, the bit line can be connected to the corresponding I/O
While placing them together for each data line,
Even if there is a defect extending over more than one column, as long as it is within a block of the same I/O data line, all defective memory cells can be replaced with memory cells in the spare column. Therefore, a redundant circuit with high defect relief efficiency can be realized while minimizing the increase in chip area and the decrease in operating speed caused by the increase in the number of bits in the memory configuration.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory device according to a first embodiment of the present invention, FIG. 2 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a semiconductor memory device according to a second embodiment of the present invention. FIG. 4 is a circuit diagram of a semiconductor memory device according to a fourth embodiment of the present invention, and FIGS. 5 and 6 are circuit diagrams of a conventional semiconductor memory device. _B1 to _B16 ...Regular bit line, _B17 to _B20 ...Spare bit line, _D1 to _D4 ...I/O data line, _F1 to _F5 ,
F ₃₀ , F ₃₃ ... Fuse, M ₁ - _{M 116} ... Regular memory cell, M ₁₇ - M ₁₂₀ ... Spare memory cell, 10 - 1
4, 20-24... Column decoder.

Claims (1)

[Claims] 1. A plurality of memory cells are arranged in rows and columns, and there are N columns (N is an integer of 2 or more) for each column address of M (M is an integer of 2 or more). a memory cell array; N I/O data lines; electrically connecting the N I/O data lines to each of the N columns having a selected column address according to the column address; a plurality of spare columns that can replace some of the columns of the memory cell array and that exist at least one column corresponding to each of the M column addresses; at least one specific I/O data line of the I/O data lines;
electrical isolation means for electrically isolating columns electrically connected to the O data line; second electrical isolation means for connecting the spare column to the specific I/O data line according to a column address; A semiconductor memory device comprising: connection means; 2. The semiconductor memory device according to claim 1, wherein the electrical isolation means and the second electrical isolation means each include a fuse. 3 The second electrical connection means connects the N I/Os according to the spare column as the column address.
N transfer gate transistors for connection to any one of the data lines; means for applying a constant voltage to the gate electrode of each of the transfer gate transistors; between the gate electrode of each of the transfer gate transistors and a reference potential point; 2. The semiconductor memory device according to claim 1, further comprising: N connected fuses. 4 The second electrical connection means connects the N I/Os according to the spare column as the column address.
N for connecting to any one of the data lines
means for applying a constant voltage to the gate electrode of each of the transfer gate transistors via an inverter; N fuses each connected between the input terminal of each of the inverters and a power supply potential point; 2. The semiconductor memory device according to claim 1, further comprising: N high resistance elements each connected between an input terminal of the inverter and a reference potential point. 5. The electrical isolation means includes at least one fuse provided corresponding to each I/O data line; by cutting the fuse for a specific I/O data line, 2. The semiconductor memory device according to claim 1, further comprising: means for fixing a related column selection signal line to an inactive state regardless of each address. 6 A plurality of memory cells are arranged in a matrix, and first and second column addresses are assigned to N×M columns (N is an integer of 2 or more) among them, and the first column The address specifies N columns out of N×M all at once, and the second column address specifies all the first columns one by one from the N columns specified by the first column address. A memory cell array in which a total of N columns are collectively designated for column addresses; N I/O data lines; and the N I/O data lines are designated as the first column address; a first electrical connection means for electrically connecting each of the N columns having a selected first column address; said N I/O data lines to said second column address; Therefore, second electrical connection means electrically connects to each of the N columns having the selected second column address; at least N columns that can replace some columns of the memory cell array; a spare column of; for at least one particular column address of said first column addresses, when said particular column address is input, acts on behalf of said first electrical connection means to connect said spare column to said first column address; Third electrical connection means electrically connecting one to each of the N I/O data lines: at least one specific I/O data line among the N I/O data lines; and a column electrically connected to the specific I/O data line in the memory cell array; a fourth electrical connection means for connecting the I/O data line to the specific I/O data line. 7. The semiconductor memory device according to claim 6, wherein the electrical isolation means and the fourth electrical connection means each include a fuse. 8 The fourth electrical connection means connects the N I/Os according to the spare column as the column address.
N for connecting to any one of the data lines
transfer gate transistors; means for applying a constant voltage to the gate electrode of each transfer gate transistor; N fuses connected between the gate electrode of each transfer gate transistor and a reference potential point; 7. The semiconductor memory device according to claim 6. 9 The fourth electrical connection means connects the N I/Os according to the spare column as the column address.
N for connecting to any one of the data lines
means for applying a constant voltage to the gate electrode of each of the transfer gate transistors via an inverter; N fuses each connected between the input terminal of each of the inverters and a power supply potential point; 7. The semiconductor memory device according to claim 6, further comprising: N high resistance elements each connected between an input terminal of the inverter and a reference potential point. 10 The electrical isolation means includes at least one fuse provided corresponding to each I/O data line; by cutting the fuse for a specific I/O data line, the electrical isolation means disconnects the specific I/O data line. 7. The semiconductor memory device according to claim 6, further comprising: means for fixing a related column selection signal line to an inactive state regardless of the column address.