JPH0454509Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to the structure of a semiconductor integrated circuit, particularly a CMOS integrated circuit.

[Conventional technology]

Conventionally, an integrated circuit in which system functions are changed by switching bus lines has, for example, three unit blocks 31, 3, as shown in FIG.
2, 33, and multiple bus lines and multiple switch circuits in switch groups 1 and 2. Functions can be changed by changing the connections between bus lines and unit blocks by switching these switch circuits. There is. In this configuration, when switch groups 1 and 2 are all tilted to side b, all functions of the integrated circuit are utilized; when switch groups 1 and 2 are all tilted to side a, The integrated circuit utilizes only the functions of two unit blocks 31 and 33.

In this case, the reason for providing the switch group 1 to switch the connection between the output of the unit block 31 and the input of the unit block 32 or the input of the unit block 33 is to reduce power consumption.

In general, CMOS integrated circuits have the property that current flows transiently when the logic state of a gate circuit reacts, and therefore power consumption increases depending on the number of times the logic state changes. Therefore, if there is no change in logic state, power consumption is reduced to a virtually negligible value.

In order to eliminate the power consumption of COMS integrated circuits by utilizing this property, signal inputs should be connected to unit blocks whose functions are no longer required and whose outputs do not need to be connected to other unit blocks. figure,
The logical state within a unit block is fixed.

Therefore, as shown in the example in Figure 6, functions can be added by switching the connection between the bus line inside the integrated circuit and each unit block by controlling a switch circuit using an external control signal. It is well known to perform deletions and deletions at any time to realize an integrated circuit that can fulfill a desired function.

By the way, in such a case, since the signal propagation path changes as the bus line is switched, the conventional switch circuit has a disadvantage in that the signal delay time differs depending on the path.

Sometimes, in an integrated circuit that performs pipeline processing as shown in FIG. 7 and changes functions using switches 37 and 38, switches 37 and 3
8, an increase in signal delay time due to a change in the path causes a decrease in the operating frequency of the integrated circuit.

Therefore, with reference to FIG. 7, the principle of pipeline processing in which system functions are changed by switching bus lines will be explained. Here, we will take a look inside the integrated circuit.
The circuit is divided into unit blocks 31, 32, and 33, between which latch circuits 34, 35, and 36 are arranged, and switches 37 and 38 are provided. The signal is
These divided sections are transferred in a bucket brigade style, improving overall processing speed. In this case, the signal delay time from the latch output to the latch input must be within a fixed time, usually within the period of the system clock. In other words, the path with the maximum delay time from the output of latch 34 to the input of latch 36 will determine the highest operating frequency of the system.

For example, when the switches 37 and 38 are tilted to the b side, the path from the switch 34 to the latch 36 is the path from the latch 34 to the unit block 32, the switch 37, and the latch 35, or the path from the latch 35 to the unit block 35. Block 33, switch 38,
This is the path leading to latch 36.

Next, when the switches 37 and 38 are turned to side a, the same path is from the latch 34 to the unit block 32, the switches 37 and 38, and the latch 36.

In this case, the change in delay time due to the difference in route due to switch switching requires a unit block of 3
Delay times 2 and 33 and switch circuits 37 and 38
This includes changes in delay time.

In particular, when the unit blocks 32 and 33 are completely the same, or when the signal processing times in the unit blocks 32 and 33 are equal, the switch circuits 37 and 3
The delay time at step 8 is a major factor in determining the upper limit operating frequency of the system.

Now, FIG. 8 shows a gate circuit that can realize the switch circuit shown in the configuration examples shown in FIGS. 6 and 7 in an integrated circuit.

NAND circuits 1 and 3 and inverter circuit 2,
The part made up of NAND circuits 4' is a 1-input to 2-output switch circuit, and the part made up of NAND circuits 5', 6', and 7' is a 2-input to 1-output switch circuit. They correspond to switch groups 1 and 2 shown in FIG. 6, or switch circuits 37 and 38 shown in FIG. 7, respectively. When the path in which the control signal is connected to node a is selected, the switch groups 1 and 2 are connected to the a side in FIG. 6, and the switches 37 and 38 are connected to the a side in FIG. , when the path in which the control signal is connected to node b is selected, switch groups 1 and 2 are on the b side in FIG. 6, and switch group 3 is on the b side in FIG.
This corresponds to a state where 7 and 38 are connected to the b side.

Now, with reference to FIG. 8, a comparison will be made of the difference in the delay time of the input signal between the case where the control signal is connected to the node a and the case where the control signal is connected to the node b in the conventional switch circuit. The path corresponding to the case where the switch is connected to side b in Figures 6 and 7 is as follows:
c→1→d→2→e or h→5'→i→7'→k
The corresponding path when the switch is connected to side a is c→3→f→4'→g→6'→j→
7'→k. The number of logic stages is two stages in both cases in the former case, and four stages in the latter case.

In FIGS. 6 and 7, the delay time of the path corresponding to when the switch is connected to side a is large, and therefore the maximum operating frequency of the system is determined by this value.

Further, since a large number of switch circuits are often used to switch bus lines, it is desirable that the area required for arranging the switch portion be as small as possible. In the example of FIG. 8, the number of gates is seven, excluding the control gate 7a, and the layout area required for arranging the gates as an integrated circuit is relatively large.

As described above, in the switch circuit according to the prior art, (1) the number of theoretical stages is large, and therefore the delay time in this part becomes large;

(2) A large number of gates are required, which increases the layout area.

It has the following drawbacks.

[Problem that the invention attempts to solve]

Accordingly, an object of the present invention is to provide a switch circuit that minimizes the number of gate stages and reduces the delay time of passing signals when switching bus lines for changing functions within an integrated circuit.

Another objective is to minimize the layout area of the switch circuit in terms of integrated circuit fabrication.

[Means for solving problems]

Therefore, this invention aims to change the functionality of the system.
When switching with a switch circuit, there is no particular consideration given to the polarity of the signal in the intermediate path, so that it is transmitted to the output terminal with the correct polarity.
It is designed to use the minimum number of gate stages required.

That is, in a semiconductor integrated circuit having a switch circuit that inserts or prevents a third functional element from being inserted between a first functional element and a second functional element, the switch circuit a first terminal to which the output of the functional element is supplied; a second terminal to which the output of the first functional element is supplied to the third functional element; and a third terminal to which the output of the third functional element is supplied.
a fourth terminal that supplies the output of the first or third functional element to the second functional element, and a NAND circuit or NOR circuit inserted between the first terminal and the second terminal. and an inverter circuit,
an inverter circuit and a clocked inverter circuit inserted between the third terminal and the fourth terminal; and a clocked inverter circuit inserted between the first terminal and the fourth terminal.
It is characterized by comprising a NAND circuit, a clocked inverter circuit, and means for controlling the NAND circuit or NOR circuit and the clocked inverter circuit.

[Effect]

As described above, according to the present invention, the number of gate stages in the switch circuit inside the integrated circuit can be reduced and the signal propagation delay time can be significantly improved.

Furthermore, since the layout area of the switch portion inside the integrated circuit can be reduced, it is extremely useful from the viewpoint of manufacturing the integrated circuit.

〔Example〕

The present invention will be described in detail below with reference to the drawings.

An embodiment of the configuration of a switch circuit according to the present invention is shown in FIG. The logic circuit composed of the inverter circuit 2 and the NAND circuits 1 and 3 is a 1-input to 2-output switch circuit, and the logic circuit composed of the inverter circuit 4 and clocked inverter circuits 5 and 6 is a 2-input to 2-output switch circuit. This is a pair-to-one output switch circuit.

The circuit from the terminal T1 to the terminal T2 in FIG. 1A can be replaced with a circuit from the terminal T1 to the terminal T2 as shown in FIG. 1B as another embodiment. Here, 1B is NOR
The circuit 2B is an inverter circuit.

The clocked inverter circuits 5 and 6 in FIG. 1 are multi-gate circuits unique to CMOS circuits, and FIG. 2 shows a circuit constructed using MOS transistors. In FIG. 2, P-type MOS transistors 21, 22 and N-type MOS transistors 23, 24 are all connected in series between the power supply and ground, and the logic on the path from signal input 2a to signal output 2d is The number of stages is one.

Now, how the present invention overcomes the drawbacks of the conventional switch circuit will be explained.

First, the reduction in the number of logic stages and the resulting reduction in signal propagation delay time will be explained with reference to FIG.

Figure 8 shows a circuit based on the conventional technology when the switch is
The path corresponding to the case of falling to the side is C → 1 → d →
2→e or g→4→h→5→i, and the corresponding path when the switch falls to side a is c→
3→f→6→i. Here, the number of logic stages is 2 stages in both cases in the former case, and 2 stages in the latter case. Compared to the prior art, the number of logic stages does not change to 2 stages in the path corresponding to the case where the switch is tilted to the b side in FIG. 8. However, in the path corresponding to the case where the switch is tilted to side a, the number of logic stages is two, which is reduced by half compared to the case of the prior art.

In a signal processing circuit, it is essential that the number of logic stages be reduced without reversing the polarity of the logic. The path c→3→f→6→i shown in FIG. 1 passes through a signal NAND circuit 3 and a clocked inverter circuit 6. They are respectively components of a 1-input to 2-output switch and a 2-input to 1-output switch.

By the way, in a single switch circuit, the polarity of the signal is reversed. That is, from node c to NAND
The polarity of the signal reaching the node f via the circuit 3 is reversed. Similarly, the polarity is similarly reversed from node f to node i. However, the important point here is that since the signal at node f is not taken into other signal processing blocks, the polarity at this point does not matter from the perspective of the entire system, and the polarity of the signal at node c is , is correctly transmitted to node i. The configuration according to the present invention satisfies this requirement and makes it possible to reduce the number of logic stages.

Part 3 about one and two embodiments applying the present invention.
This will be explained using FIGS. 4 and 5. FIG. 3 shows an example of the configuration of a digital filter used for digital processing of television signals.

Figure 4 shows time axis compression multiplexing (hereinafter referred to as TCI)
This is an example of a circuit configuration that provides a gap on the time axis between two multiplexed signal components for signal processing. FIG. 5 is a waveform diagram for supplementary explanation of the operation of the circuit shown in FIG. 4.

FIG. 3 is a diagram showing the configuration of a digital filter integrated circuit using the present invention.

The logic circuits to which this invention is applied are NAND circuit 1,
3, inverter circuits 2 and 4, and clocked inverter circuits 5 and 6,
Multipliers 8, 9, 10 and adders 12, 14, 1
6, 18 and latch circuits 11, 13, 15, 1
It is used to switch arithmetic units in an integrated circuit including 7 and 19.

The signal input is connected via node C to the inputs of multipliers 8, 9, 10. The output of multiplier 8 is connected to latch 11 and adder 18 via node d.
The output of the multiplier 9 is passed through the node e to the adders 12 and 1.
6 input. The output of multiplier 1 is connected to the input of adder 14 via node f. Further, the switch circuit according to the present invention surrounded by a dotted line in the figure connects the output of the adder 12 via the node i, the latch 13 via the node k, the output of the adder 16 via the contact O, and the output of the adder 12 via the node i. Latch circuit 1 through
7 are connected to each other.

Next, the operation of the digital filter shown in FIG. 3 will be explained. The digital filter with this configuration is called a transversal type digital filter, and includes latch circuits 11, 13, 15, 1.
Pipeline processing is performed using circuits 7 and 19, and the function of the filter, that is, the order is changed by switching the switch circuit surrounded by the dotted line.

The change in order will be explained in more detail. When the control signal selects the route connected to the node b by the inverter circuit 7a, the signal input is transmitted to the multipliers 8, 9, 1.
0 by the coefficients H2, H1, and H0, respectively, and output to nodes d, e, and f. Next, the signal moves from node d→h→i→j→k→l→m→n→o→p
It is output via →r→s→t→u. During this time, the signal is repeatedly multiplied and added by pipeline processing. The filter characteristics achieved by this process are expressed using Z changes as follows: H(Z)=Z{H+H(Z+Z)+H(Z+Z)}
...(1), and it can be seen that the order is 5th.

Next, when the control signal selects the path connected to node a by the inverter circuit 7a, the signal input becomes
Coefficients H ₂ and H are multiplied by multipliers 8 and 9, respectively,
It is output to nodes d and e. Then, node d→h→
It is output via i→q→r→s→t→u.
If the filter characteristics realized by processing in this path are similarly expressed by Z transformation, it becomes H(Z)=Z{H+H(Z+Z)}...(2), which shows that the order is cubic. .

As described above, the switch circuit of the present invention is applied to order switching, which is one of the important functions of a digital filter, and the speed of the digital filter is increased.

Next, FIG. 4 is a diagram showing the configuration of a TCI signal gap processing circuit as another embodiment to which the present invention is applied. The logic circuit applying this invention is
NAND circuits 1 and 3, inverter circuits 2 and 4,
7a, and clocked inverter circuits 5 and 6, which shapes a desired signal waveform using a delay line 28 and a gap processing circuit 29.

The switch circuit according to the present invention, which is surrounded by dotted lines in the figure, receives a signal input through node C, and a node e,
It is connected to the delay line 28 via f and to the input of the gap processing circuit 28 via node i. The signal output is connected to the output of the clearance processing circuit 29 via node j.

The operation of the circuit configuration shown in FIG. 4 will be explained with reference to FIG. The figure shows temporal changes in signals at nodes a, b, c, h, g, i, k, and j shown in FIG. 4 in order from the top.

First, when the control signal 1 selects the path connected at node a by the inverter circuit 7a, the signal input goes from node C to node h via the NAND circuit 3.
5, resulting in a signal waveform shown in FIG.

Next, when the control signal 1 selects the path connected at node b by the inverter circuit 7a, the signal input is from node c → node d → node e → delay line 28 → node f
The signal is transmitted to the node g via the node g, resulting in a signal waveform shown in FIG. This signal is obtained by adding a portion of signal 1 delayed by time Δt to a portion of signal 2 delayed by delay time Δt by the delay line 28.

Next, the signals at nodes h and g are combined by clocked inverter circuits 5 and 6, which are components of the switch circuit, and transmitted to node i, resulting in the signal waveform shown in FIG. 5.

Further, from the signal at node i, a delayed portion of the component of signal 1 is removed in a gap processing circuit 29, and the signal is provided to node j as a signal output. As shown in FIG. 5, this output signal has a gap time Δt between signal 1 and signal 2.

The gap time is provided, for example, in a signal processing circuit such as a filter to avoid interference between signals 1 and 2.

As mentioned above, delay time switching, which is one of the important functions of the time axis clearance processing device required for processing TCI signals,
Applying the switch of this invention, processing is performed at high speed.
This makes it possible to realize TCI signal processing circuits.

(Effect of the invention) Here, a plurality of functional blocks are connected by a bus line, and in order to change the function of the integrated circuit by switching the bus line connecting the functional blocks, it is used inside the integrated circuit. We will explain how the performance of the switch circuit was improved by implementing the present invention.

Comparing the number of gate stages in the switch circuit between FIG. 1 and FIG. 8, the conventional technology has a maximum of 4 stages, and the technology according to the present invention has a maximum of 2 stages.

Eliminating the number of gate stages leads to increased operating speed of integrated circuits. As an example, CMOS with design standard 2μm
Let's take the case of In this case, since the average delay time of the gate circuit is 1 nanosecond, the maximum delay time in the switch circuit is 4 nanoseconds in the prior art, but 2 nanoseconds in the technology of the present invention. In other words, the delay time can be improved by 2 nanoseconds.

Next, the layout area of the switch portion in the integrated circuit will be compared based on FIG. 1 and FIG.

Comparing the number of gates in the signal processing circuit excluding the control gate circuit, in the conventional technology, it is 1, 2,
What used to be seven pieces, 3, 4', 5', 6', and 7',
In the technology according to the present invention, 1, 2, 3, 4, 5, 6
It can be reduced to 6 pieces.

Generally, since a bus line is made up of a plurality of signal lines, the number of switch circuits connected thereto also inevitably increases. Therefore, it is desirable that the bus line switching switch circuits used in large numbers in an integrated circuit have as small an area as possible.

Since the number of gates and the layout area are almost in a comparative relationship, the technology according to the present invention can reduce the layout area of the switch circuit part to 6/7 compared to the conventional technology.
This is effective for reducing the chip area of the integrated circuit.

[Brief explanation of the drawing]

FIG. 1A is a logic circuit diagram showing an embodiment of the configuration of a switch circuit according to the present invention, and FIG.
FIG. 2 is a circuit diagram for explaining the clocked inverter circuits 5 and 6 shown in FIG. ₁ , and FIG. 3 is a logic circuit diagram showing another embodiment of the circuit from terminal _T1 to terminal T2. 4 is a logic circuit diagram showing an embodiment in which the present invention is applied to the configuration of a digital filter; FIG. Fig. 5 is a signal waveform diagram for explaining the operation of the circuit shown in Fig. 4, Fig. 6 is a block diagram showing an example of the configuration of an integrated circuit in which system functions are changed by switching bus lines, and Fig. 7 is a signal waveform diagram for explaining the operation of the circuit shown in Fig. 4. A block diagram illustrating the principle of changing system functions by switching bus lines, and FIG. 8 is a logic circuit diagram showing an example of the configuration of a conventional switch circuit. 1, 3, 5', 6', 7'...NAND circuit, 1B
...NOR circuit, 2,2B,4',7a...Inverter circuit, 5,6,20...Clocked inverter circuit, 8,9,10...Multiplier, 12,1
4, 16, 18... Adder, 11, 13, 15,
17, 19...Latch circuit, 21, 22...P type
MOS transistor, 23, 24...N-type MOS transistor, 28...Delay line, 29...Gap processing circuit, 31, 32, 33...Unit block, 3
4, 35, 36...Latch circuit, 37, 38...
switch circuit.

Claims (1)

[Claims for Utility Model Registration] There is a third functional element between the first functional element and the second functional element.
In a semiconductor integrated circuit having a switch circuit for inserting or not inserting a functional element, the switch circuit has a first terminal to which an output of the first functional element is supplied; a second terminal that supplies the output of the first functional element to the functional element; a third terminal that supplies the output of the third functional element to the functional element of the first or third functional element; a fourth terminal that supplies an output to the second functional element; a NAND circuit or a NOR circuit and an inverter circuit inserted between the first terminal and the second terminal; and the third terminal. an inverter circuit and a clocked inverter circuit inserted between the terminal and the fourth terminal; a NAND circuit and a clocked inverter circuit inserted between the first terminal and the fourth terminal; 1. A semiconductor integrated circuit comprising means for controlling a NAND circuit or a NOR circuit and a clocked inverter circuit.