JPH0454575A - Parallel computer - Google Patents

Abstract

PURPOSE:To increase the capacity of a memory that can be directly referred to, to decrease the processing steps, and to shorten the processing time by separating the memory from each arithmetic part and setting the memory between the arithmetic part to directly refer to the memory. CONSTITUTION:When an arithmetic part P carries out a single instruction, plural means P refer to one of plural memory means M and take the data out of the means M to apply to processing to this means in parallel with each other. This processed result is stored in a certain means M. If the sum total is obtained at the periphery of a grating 4 in the image processing, for example, the means M are arrayed in a grating shape and the means P are set at each intersecting point between the diagonal lines of the grating. Then the image data are stored in the means M in response to the picture elements. The data stored in the means M near the grating 4 are referred to be the periphery means P and added together. Thus the sum total of data is obtained. Thus the due processing is attained just with the direct reference given to plural means M, and the processing speed is increased.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a single-instruction parallel computer that processes a single instruction in parallel, and particularly to a parallel computer that directly references multiple memories from an arithmetic unit.

[Conventional technology]

Single-instruction type parallel computers are used in devices such as image processing devices that process large amounts of data by repeating simple operations, and parallel processing enables high-speed operations on large amounts of data.

FIG. 4 is a schematic block diagram showing the general configuration of a single-instruction type parallel computer, in which a plurality of calculation units P, P... and memories M, M... are connected in parallel to the control device 20. has been done. The control device 20 generates instructions and addresses,
The same instruction is given to each arithmetic unit P, P..., and the same address used for executing the instruction is assigned to the memories M, M...
give to...

Arithmetic unit P and memory IJ of a conventional single-instruction parallel computer
An example of the connection structure with M is as shown in FIG. 5, where the calculation units P, P... are arranged in a grid pattern, and each calculation unit P, P... has its own dedicated memory M, It has M... Furthermore, the configuration of the calculation units P, P, etc. is as shown in FIG.
It is composed of a communication device 11 that controls communication with...

[Problem to be solved by the invention]

In parallel computers, increasing the processing speed is an important issue, and for this purpose it is necessary to reduce the number of data processing steps. In a conventional single-instruction type parallel computer configured as described above, each calculation unit is limited to referencing only its own dedicated memory, so each calculation unit directly references the memory of other calculation units. If the memory cannot be accessed and referenced, the memory is referenced indirectly through communication.

In other words, communication was performed with a calculation unit having the memory and a calculation unit located between the calculation unit, and the memory was referenced via them. For example, when performing a summation calculation of 4 neighboring grids, which is often used in image processing, each calculation unit communicates with 4 calculation units corresponding to 4 neighboring pixels, and obtains the values of the 4 neighboring pixels stored in their memory. was. Therefore, there is a problem in that many processing steps are required for reference, resulting in a long processing time.

The present invention was developed in view of the above circumstances, and it increases the number of memories that can be directly referenced by separating memory from each calculation unit and placing it between multiple calculation units so that they can be directly referenced. The purpose of this invention is to provide a single-instruction type parallel computer that can reduce processing steps and shorten processing time.

[Means to solve the problem]

A parallel computer according to the present invention is a parallel computer that processes a single instruction in parallel, and includes a plurality of arithmetic means for executing the single instruction, and a plurality of memory means directly referenced by each arithmetic means, Each memory means is characterized in that it is designed to be directly referenced by a plurality of calculation means.

[Effect]

In the present invention, when the arithmetic means executes a single instruction,
the plurality of calculation means refer to one from the plurality of memory means,
Data is extracted from there, processed in parallel, and the processed results are stored in any memory means. For example, in image processing, when calculating the sum of 4 neighboring grids, the memory means are arranged in a grid, the calculation means are arranged at the intersections of the diagonals of the grid, and the image data is stored in the memory means corresponding to the pixels. , the data stored in the four neighboring memory means can be sequentially referred to and added by the neighboring calculation means to obtain the total sum. Therefore, processing can be performed simply by directly referencing a plurality of memory means, so that processing speed can be increased.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of a parallel computer according to the present invention, and FIG. 2 is a block diagram showing the configuration of an arithmetic unit. In the figure, P is an arithmetic unit which is an arithmetic means, and as shown in FIG. It is provided with a communicator 11 for communicating with the memory, a selector 13 for selecting a memory to be referred to, and a 2-bit direction flag register 12 for outputting a selection signal to give an instruction to the selector 13. Each arithmetic unit P is connected to four communication paths capable of bidirectional communication, and the selector 13 switches the communication paths. The calculation units P, P... are arranged in a grid, and memos IJM, M are placed at the intersections of the diagonals of the grid.
...is placed. Each memory M is connected to four communication paths capable of bidirectional communication, and each calculation unit P
and memory M are interconnected at their respective four neighborhoods along the diagonal line.

Further, the selector 13 normally selects a communication path based on a signal from a single control device, and selects a communication path for all calculation units P.

Nearby memories M, M... in the same direction in P...
See. On the other hand, when each calculation unit P refers to memories M, M, etc. in different directions, the calculation unit 10 sets the value in the diagonal direction of the memories M, M, etc. to be selected in the direction flag register 12 (for example, Upper right is “OO”, lower right is “01’”
'', the upper left is set to "10", and the lower left is set to "11"), and the selector selects the communication path based on the values.

Next, the operation of the parallel computer according to the present invention will be explained using an example in which the sum of the 4 neighboring grids is calculated. FIG. 3 is a diagram illustrating the calculation procedure of the summation, and the summation of four neighboring parts is obtained in three steps, steps S1, S2 and S3.

In step S1, the calculation unit P adds the value V + (or ■.) stored in the upper right memory M and the value V 2 (or V3) stored in the lower left memory M. or ■.+V3) is stored in the memory M at the lower left of each. V, +V2 and V stored in the upper left memory M and the lower right memory M in the next step S2. +V, and are added in the arithmetic unit P between them, and the addition result (V,
10V2+V. +V3) is stored in the lower right memory M.

This is the sum of the neighborhood of grid 4, but since this is the sum of the neighborhood of grid 4 of the memory just one above, step S3
Then, the calculation unit P reads the value of the lower left memory M, stores it again in the upper left memory M, and transfers the sum to the memory M one level above.

By performing the above steps for all the calculation units P, P, . . . , the total sum in the vicinity of the grid 4 can be obtained.

In the single-instruction type parallel computer of the present invention, when an operation is performed between nearby memories directly connected to an operation section, the operation section directly refers to data in the memory without using a communication function. In the conventional case, when referencing a memory other than the local memory specific to an arithmetic unit, it was necessary for neighboring arithmetic units to refer to that memory and exchange data using a communication function, but with the present invention, this is not possible. That step is not necessary. Therefore, as mentioned above, the sum of the neighborhood of grid 4 can be found in 3 steps with the parallel computer of the present invention, but in the conventional system, if communication and calculation of operands used in calculations are counted as 1 step and 7 steps, it takes 4 steps. It becomes necessary.

Furthermore, data operations between neighbors are usually time-consuming, so if the memory between neighbors can be directly referenced, as in the parallel computer of the present invention, processing speeds up. Furthermore, in a calculation between neighbors, a calculation is performed on a plurality of operands, and the operands are located in the memory, and arranging the calculation unit between the memories is a rational configuration for the calculation.

Furthermore, the complexity of the data lines used in this configuration is comparable to the complexity of the data lines used in mutual communication networks in the vicinity, and mutual communication between the calculation units in the vicinity can be performed via the memory between them. Therefore, a communication network between neighbors can be omitted.

In addition, the selection of the communication path by the selector is made possible not only by the selection signal from a single control device, but also by setting a value in the direction flag register in the calculation unit, so each calculation unit can independently refer to a different address. I can't do it, but
Each calculation unit can independently refer to relatively different memories,
The same effect as referring to substantially different addresses can be obtained.

In this embodiment, the memories and calculation units are arranged in a grid pattern, but the arrangement of the present invention is not limited to this, and may be any two-dimensional or three-dimensional arrangement such as n-launch, butterfly network, piper cube, etc. Needless to say, it is possible to use

〔effect〕

As explained above, in the present invention, in addition to arranging a plurality of memory means that can be directly referenced by a plurality of calculation means,
Since the memory means is configured so that it can be directly referenced by multiple calculation means, it is possible to perform high-speed processing of a single instruction using multiple operands without complicating the hardware configuration by omitting steps required for communication. It produces the same effect as possible.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing the configuration of a parallel computer according to the present invention, FIG. 2 is a block diagram showing the configuration of the calculation section, FIG. 4
The figure is a schematic block diagram showing the general configuration of a single-instruction type parallel computer, Figure 5 is a block diagram showing the configuration of a conventional single-instruction type parallel computer, and Figure 6 is a block diagram showing the configuration of a conventional single-instruction type parallel computer. FIG. 2 is a block diagram showing the configuration. P...Arithmetic unit M...Memory patent Applicant Sumitomo Metal Industries Co., Ltd. Agent Patent attorney Noboru Kono Figure] 2 Figure Figure Figure Figure

Claims (1)

[Claims] 1. A parallel computer that processes a single instruction in parallel, comprising: a plurality of arithmetic means for executing the single instruction; and a plurality of memory means directly referenced by each arithmetic means; A parallel computer characterized in that each memory means is designed to be directly referenced by a plurality of calculation means.