JPH0454636A - processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a processor that decodes and executes instructions, and relates to a technique that is effective when applied to, for example, a single-chip microcomputer.

[Conventional technology]

A processor includes an instruction briefetch unit that briefetches instructions, an instruction decode unit that decodes instructions, and an execution unit that executes instructions according to the instruction decode results. In order to make this possible, some devices have various built-in cache memories and can perform advanced pipeline processing. There are also processors that have a self-debug function that allows user programs to be debugged without the use of dedicated hardware (emulator). These self-debug functions include instruction operand break and step trace, which are enabled by setting a bit in the processor status word.

An example of a document describing such a processor is ``rH32/200 Operation Architecture Manual (Third Edition)'' published by Hitachi, Ltd. in June 1988.

[Problem to be solved by the invention]

However, according to the inventor's study of conventional processors, the following problems were found.

That is, in debugging using the self-debug function, instruction execution may become an infinite loop due to a program error, and it is difficult to escape from this infinite loop.

Furthermore, in the step trace of the self-debug function, debug exception handling is always performed every time one instruction is executed, so real-time performance is important. Conventional self-debugging functions are considered inappropriate for debugging user systems and their programs. In order to improve real-time performance, it is possible to trace only desired instructions, but to make this possible there is an inconvenience such as the need to replace instructions in the user program. It is possible to use dedicated hardware for self-debugging in order to improve real-time performance, but if the CPU (Central Processing Unit) is faster and has higher functionality such as a built-in cache memory, dedicated hardware may be used. The reality is that it is difficult to develop a debugger with hardware.

Furthermore, according to the self-debug function's instruction operand break, the number of breakpoints that can be set is limited because the size of the breakpoint setting register is limited, making it difficult to use for debugging large programs. It is said that

As described above, the present inventors have clarified that in conventional processors, the self-debug function may be difficult to use depending on the user program, and that it does not necessarily improve the efficiency of debugging for software development. .

An object of the present invention is to provide a technique that can improve the efficiency of debugging for software development.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

That is, there is a selection means for selecting a processing routine for a result of decoding a specific instruction as either a first process or a second process different from the first process, and an instruction means for providing selection information to this selection means, or an external instruction to this selection means. A processor is configured by providing an external terminal that allows selection information to be supplied.

Here, the above first process is a non-debug process, and the above second process is a non-debug process.
The processing can be treated as debugging processing.

In addition, the above specific command can be used as a jump command,
In such a case, a processing routine that is at least one nest level ahead from the jump destination specified by the jump instruction can be used as the debugging process. Furthermore, the selection means can also be a microaddress sequencer that specifies a microinstruction address.

[For production]

According to the above means, the first processing routine for the decoding result of the specific instruction is executed based on the selection information given from the outside by the instruction means or via the external terminal.
It is possible to select either the process or a second process different from the above process. This makes it easy to escape from an infinite loop of instruction execution caused by a program error. In addition, instead of generating debug exceptions for each instruction, generating debug exceptions by selectively switching the processing routine for a specific instruction improves the real-time performance of debugging, and furthermore, it improves the real-time performance of debugging. Improve debugging efficiency by eliminating the need to set breakpoints.

〔Example〕

FIG. 2 shows a microcomputer which is an embodiment of the present invention. The microcomputer shown in the figure is formed on a single semiconductor substrate, such as single crystal silicon, by a known semiconductor integrated circuit manufacturing technique, although this is not particularly limited.

The instruction briefetch unit 2 has a built-in instruction cache memory, and performs instruction briefetch independently of instruction execution. If the instruction cache is hit, no external memory is accessed. Furthermore, in order to speed up branch instructions, four branch windows are formed, although this is not particularly limited, and when a hit occurs in one of the four branch windows, fetching of the branch destination instruction is simplified. Further, an input/output control unit 13 coupled to the external data/address bus controls the output of instructions and operands, and an instruction decode unit 5 decodes fetched instructions. This decoding result is passed to the subsequent control unit 6, and the execution unit 8 is controlled. This causes the fetched operand to be processed. The processed operands are transferred again to the input/output control unit 13 and stored in external memory. Furthermore, access to the external memory is performed through checking of protection conditions and address conversion by the memory management unit 11. Since this is performed in parallel with instruction execution processing, no performance overhead occurs.

FIG. 1 shows a more detailed configuration of the main parts of the microcomputer shown in FIG. 2.

The instruction decode unit 5 includes the input/output control unit 1.
an instruction register 5A that holds the instructions transferred from 3;
It also includes an instruction decoder 5B that decodes the output held by the instruction register 5A. The decoded output of this instruction decoder 5B is used as the start address of a microinstruction to be described later.

The control unit 6 includes a microprogram ROM (read-only memory) 6 that stores microprograms.
B, a micro-address sequencer 6A that specifies the micro-instruction address of this ROM 6B, and a micro-instruction decoder 6D that decodes the micro-instruction 6C read out from the micro-program ROM 6B. The decoded output of the decoder 6D is supplied to each section as a control signal 6E, and the next microaddress information included in the microinstruction read immediately before is taken into the microaddress sequencer 6A.

That is, the microaddress sequencer 6A reads a series of microinstructions from the microprogram ROM 6B based on the start address of the microinstruction from the instruction decoder 5B and the next microaddress information from the decoder 6D.

The microaddress sequencer 6A is provided with a selection function for selecting a processing routine for a result of decoding a specific instruction as either a first process or a second process different from the first process.
This is realized by the read address control of OM6B. Although not particularly limited, the specific instruction is a JSR (jump subroutine) instruction, the first process is a non-debug process, and the second process is a debug process. The non-debug processing referred to herein is the original processing of the JSR instruction, and the debug processing is defined as exception processing for debugging, which will be described in detail later. Also, whether the first process (non-debug process) is selected by this microaddress sequencer 6A,
Whether the second process (exception process) is selected is determined by the state of a status flag register 8B in a register block 8A, which will be described later. That is, in this embodiment, the state of the state flag register 8B is the above-mentioned first. This is used as selection information for the second process. There is no particular restriction, but if the status flag is d
When i Ot+, non-debug processing is selected, and when it is 1'', debug processing is selected.

The execution unit 8 has a register block 8A consisting of a plurality of registers and an arithmetic unit block 8C including an ALU (arithmetic logic unit), which are connected to an internal bus 17.
It is possible to exchange data with other blocks connected to the internal bus 17.

Here, the instruction execution control section in the present invention is constituted by the control unit 6 and the execution unit 8.

3 and 4 show an example of an application executed by the processor of this embodiment.

When the flag state of the state flag register 8B is t O+'', it is set to the normal state, and the original processing of the JSR instruction is performed by fetching the JSR instruction.

That is, when the flag state is It OII, according to the microinstruction read by the sequencer 6A, the value of the program counter PC in the register block 8A is first saved to the stack pointer SP in the same block 8A, and the subroutine address d is It is entered into the program counter PC. This causes a transition from the main routine to the subroutine.

On the other hand, the flag state of the state flag register 8B is II I
In case of II, it is placed in a debug state and debug processing is performed by fetching JSR instructions. That is, when the flag state is 11111, the value of the program counter PC is saved to the stack pointer SP, the subroutine address d is saved to the stack pointer SP, and the debug exception address V is placed to the program counter PC.

As a result, the main routine is moved to debug exception handling, and after predetermined exception handling, the process is moved to subroutine processing, and then the main routine is returned. In other words, debug exception handling is performed as a processing routine one nest level ahead from the jump destination specified by the JSR instruction. Of course, depending on how the settings are made, it is also possible to set the processing routine to be two or more nest levels ahead.

FIG. 5 shows an example of the debug exception handling routine.

Transferred to the debugger processing program by the debug exception vector. First, the contents of the user register are saved (step 5TI), the state when the user program is stopped is displayed (break display) (step 5T2), a debugger command is input (step 5T3), and the command is analyzed. (Step ST4.ST7,
5T9). That is, it is determined whether or not to re-execute the user program (step 5T4), and if it is determined in this determination that it is not re-execution, it is determined whether or not memory display is to be performed (step 5T7). In this determination, if it is determined that "N'" is not a memory display, a determination is made as to whether or not the memory is to be changed (step 5T9).
In this case, if it is determined that "IIN" is not a memory change, another determination is made, and the debugger command is analyzed in this way.Then, in the determination in step ST4 above, "IIY" is a re-execution. If it is determined, the state setting for re-execution of the user program is performed (step 5T5), and the contents of the user register saved in step ST1 are restored (step 5T).
6), execution of the debugger program is ended. Further, if it is determined in the determination in step ST7 that the memory display is #Y II, memory contents display processing is performed (step 5T8), and further, in the determination in the step ST9 above, II Y jj that is memory change is determined.
If it is determined that this is the case, a memory change process is performed (step 5T10), and then the input in step ST3 is performed.

According to this embodiment, the following effects can be obtained.

(1) Depending on the flag state of the status register 8B, the processing routine for the decoding result of a specific instruction can be changed from non-debug processing to debug processing, and debug exception handling is generated for each instruction like the conventional step trace. Therefore, the real-time performance of debugging can be improved.

(2) Furthermore, in the debugging process in the above embodiment, there is no need to set breakpoints in predetermined registers as in the case of conventional self-debugging functions, and even if the scale of the program to be debugged is large, breakpoints can be broken in relation to registers. Since the number of points is not limited, it is considered an effective debugging function.

(3) Due to the effects of (1) and (2) above, it is possible to efficiently debug a program to be debugged even if there is no hardware (emulator) dedicated to debugging.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above-mentioned examples, and can be variously modified without departing from the gist thereof.

For example, in the above embodiment, the specific instruction is described as a JSR instruction, but an RTS (return subroutine) instruction or other instructions may be used instead of the JSR instruction. In particular, when using a conditional branch instruction, if the processing routine of this conditional branch instruction can be transitioned to processing similar to a subroutine jump (JSR) instruction depending on the state of the status flag, it is necessary to Even in the case of an infinite loop, it is possible to easily escape from the infinite loop by setting the status flag and transitioning to processing similar to JSR instruction execution.

Further, in the above embodiment, the flag is set in the status flag register 8B, but the selection information of the processing routine may also be given from the outside using an external terminal of the processor. In this case, the status flag register 8B is unnecessary.

Furthermore, selection of a processing routine based on the result of decoding a specific instruction can be used for testing the processor, self-error detection, and the like.

For example, it would be effective to change the NOP (invalid) instruction to a software interrupt instruction by selecting a processing routine, or it would function as a coprocessor instruction when a coprocessor is actually used for debugging processor instructions. , it is also effective to make it an instruction to call a debug routine if it does not exist.

In the above explanation, the invention made by the present inventor was mainly applied to a single-chip microcomputer, but the present invention is not limited thereto, and can also be applied to a microcomputer formed on a single board. I can do it. The present invention can be applied to at least a device equipped with an instruction execution control unit that executes decoded instructions.

〔Effect of the invention〕

A brief explanation of the effects obtained by the typical inventions disclosed in this application is as follows.

That is, based on selection information externally provided by an instruction means or via an external terminal, the processing routine for the decoding result of a specific instruction can be divided into a first processing and a different processing routine, without changing the program to be debugged. 2, it is easy to escape from an infinite loop during debugging. Also, since debug exception handling is not generated for each instruction, debugging can be performed in real time, and breakpoint setting registers are By eliminating the need to set breakpoints in registers, even if the program to be debugged is large in size, the number of breakpoints is not limited by the relationship with the registers. Thereby, debugging efficiency can be improved without using hardware dedicated to debugging.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the main parts of a microcomputer according to an embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of a microcomputer according to the present invention, and FIGS. 3 and 4 are diagrams showing a microcomputer according to an embodiment of the present invention. An explanatory diagram of an example of an application to be executed. FIG. 5 is a flowchart showing an example of debug exception handling in the above application. DESCRIPTION OF SYMBOLS 1... Microcomputer, 2... Instruction brief fetch unit, 5... Instruction decode unit, 5A.
...Instruction register, 5B...Instruction decoder, 6...
Control unit, 6A...Micro address sequencer, 6B...Micro program ROM, 6D...Micro instruction decoder, 8...Execution unit, 8A...
Register block, 8B...Status flag register, 8
C... Arithmetic unit block, 13... Input/output control unit.

Claims (1)

[Scope of Claims] 1. In a processor including an instruction execution control unit that decodes an instruction and executes the instruction in accordance with the instruction, the instruction execution control unit performs a processing routine for a result of decoding a specific instruction as a first process. A processor characterized by comprising: selection means for performing a second process different from the second process; and instruction means for providing selection information to the selection means. 2. In a processor including an instruction execution control unit that decodes an instruction and executes the instruction in accordance with the instruction, the instruction execution control unit divides a processing routine for the decoding result of a specific instruction into a first process and a second process different from the first process. 1. A processor comprising: selection means for either processing; and an external terminal that allows selection information to be supplied from the outside to the selection means. 3. The processor according to claim 1 or 2, wherein the first process is a non-debug process and the second process is a debug process. 4. The processor according to claim 1, 2 or 3, wherein the specific instruction is a jump instruction, and the debugging process is a processing routine at least one nest level beyond the jump destination specified by the jump instruction. 5. Claims 1, 2, and 3, wherein the selection means is a microaddress sequencer that specifies a microinstruction address.
or the processor according to 4.