JPH0454650A - Memory circuit - Google Patents

Abstract

PURPOSE:To reduce the leakage current in an SRAM at the time of stand-by by forming a cell part of the SRAM so that it keeps high temperature high a small current leakage and boosting a voltage of the SRAM part only at the time of access by using a boosting circuit as for an ascent portion of an operating voltage. CONSTITUTION:As for an SRAM 3, a threshold voltage of a transistor higher than other component in order to reduce a leakage current. At the time of stand-by, as for the SRAM of a regular CMOS structure, when a voltage being higher than a value obtained by adding a threshold voltage of a Pch transistor and a threshold voltage of an Nch transistor is applied, a data breakdown does not occur. In reality, data is held even at an extremely minute voltage lower than it, and at the time of stand-by, it is unnecessary to boost a power source system of the SRAM 3. Accordingly, a boosting circuit 4 executes boosting only at the time of accessing the SRAM 3, and when it does not access the SRAM0 3, the same voltage as other component is supplied to the SRAM 3.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory circuit, and particularly to a memory circuit that requires operation at low voltage and low current consumption.

[Conventional technology]

As shown in FIG. 3, a conventional memory circuit includes an SRAM II for storing data, and a SRAM II that supplies a write signal, a read signal, and a standby signal to the SRAM II.
A control circuit 13 that controls the RAM II, an input/output circuit 12 that inputs and outputs data to and from the outside, a path line 14 that transfers data or each signal, and the SRAM II,
Input/output circuit 12. It has a power supply circuit 15 that supplies power to the control circuit 13.

Next, the operation of the SRAM section will be briefly explained.

When writing data to SRAMII, the write signal and address are sent from the control circuit 13 via the pass line 14 to S
The write data given to RAMII is sent from the control circuit 13 or the input/output circuit 12 to the SRA via the pass line 14.
Transferred to MII. In the case of reading, the SR is similarly controlled by a signal from the control circuit 13 via the pass line 14.
AMII and control circuit 13. This is done between the input/output circuit 120.

At this time, all processing is performed under the same voltage supplied from the power supply circuit 15.

[Problem to be solved by the invention]

This conventional memory circuit has the problem of large current consumption at high temperatures for the following reasons.

Normally, the leakage current per one bit of an SRAM cell is about several PA at room temperature. When this is considered in a 16-bit SRAM, the leakage current in the entire SRAM is about several tens of nA. Next, considering the temperature characteristics, this leakage current value is 85
It increases by several tens to hundreds of times around ℃ (-industrial standard), and in the worst case it becomes several tens of μA. This phenomenon occurs because the threshold voltage of the transistor decreases as the temperature rises, and the off-leakage current increases.When considering that it is built into a microcomputer, the current consumption during standby of a battery-powered microcomputer is several seconds. μ
Since it needs to be about A, it will not meet the specifications at high temperatures. It is conceivable to raise the threshold voltage to reduce the leakage current of the transistor in the cell, but then writing and reading at a low voltage becomes impossible. Therefore, a microcomputer that operates at low voltage, maintains low current consumption even at high temperatures, and incorporates a large capacity SRAM cannot be realized using conventional technology.

[Means for Solving the Problems] The memory circuit of the present invention has an SR for storing data.
It includes an AM, a transformer circuit for configuring a power supply system dedicated to the SRAM, and a control circuit that controls the transformer circuit.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

(This example describes the case where it is built into a microcomputer.) The control circuit 1 has a microphone 0':+
7. Each component within the fuser is controlled via path line 2. The SRAM 3 performs writing, reading, and standby operations in response to signals from the control circuit 1. The booster circuit 4 boosts the voltage from the power supply circuit 5 according to a signal from the control circuit 1 and supplies the boosted voltage to the SRAM 3 . Peripheral circuit 6 performs arbitrary operations based on signals from control circuit 1. Here, in order to reduce leakage current, the threshold voltage of the transistor of the SRAM 3 is higher than that of other components, and the threshold voltage of the parts other than the SRAM 3 is low, and it is assumed that the threshold voltage is sufficiently high for low voltage operation. Therefore, writing and reading cannot be performed in the SRAM 3 of this embodiment unless the voltage is higher than that in other parts. Therefore, when writing to SRAM3 and when reading data from SRAM3, voltage sufficient to access SRAM3 is supplied by booster circuit 4. Next, the standby time will be explained. Normally, an SRAM with an 0MO8 structure will not cause data destruction if a voltage greater than the sum of the threshold voltage of the Pch transistor and the threshold voltage of the Nch transistor is applied. (Actually, data can be retained even at a very small voltage lower than that.) Therefore, there is no need to boost the power supply system of the SRAM 3 during standby. Therefore, the booster circuit 4 boosts the voltage only when the SRAM 3 is accessed, and supplies the same voltage to the SRAM 3 when the SRAM 3 is not accessed.

FIG. 2 shows a block diagram of the second embodiment. A control circuit 1 controls each component via a path line 2. SRAM3 is written by a signal from control circuit 1,
Performs read and standby operations. The voltage regulator 7 reduces the voltage from the power supply circuit 5 in response to a signal from the control circuit 1 and supplies it to the SRAM 3. The difference in structure between this embodiment and the previous embodiment is that a voltage regulator is provided in place of the booster circuit in the previous embodiment. In the second embodiment, we focused only on the difference between the required voltage for writing or reading SRAM3 and the data retention voltage, and
When accessing M3 (during writing, reading), the voltage from voltage circuit 5 is applied as is, and during standby (
data retention), the voltage from the voltage circuit 5 is reduced by the voltage regulator 4 and applied to the SRAM 3.
3. This reduces the leakage current that flows through the circuit.

〔Effect of the invention〕

As explained above, the present invention has a structure in which the SRAM cell section has a structure with low leakage current even at high temperatures, and uses a booster circuit to compensate for the increase in operating voltage by increasing the SRAM cell area only during access.
Since I increased the voltage of the M part, the SRA during standby
This has the effect of reducing leakage current at M.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment, and FIG. 3 is a block diagram of a conventional example. 1.13...control circuit, 2,14...
Pass line, 3, 11...SRAM, 4...
... Boost circuit, 5.15 ... Power supply circuit, 6.
... Peripheral circuit, 7 ... Voltage regulator, 12 ... Input/output circuit. Agent Patent Attorney Shinkan Uchihara

Claims (1)

[Claims] A memory circuit comprising an SRAM for storing data, a transformer circuit for configuring a power supply system dedicated to the SRAM, and a control circuit for controlling the transformer circuit.