JPH0454705A - Phased array antenna system - Google Patents

Abstract

PURPOSE:To reduce the fluctuation of power consumption of a phase shifter driver without changing a beam direction by adding or subtracting a proper phase shift to each of phase shift values of each antenna element. CONSTITUTION:Number of 1s of a bit string of a phase shift in M bits of N sets of antenna elements being an output of a phase shift calculation circuit 2 is counted by up/down counters 81-8N, a phase shift in a minimum unit of digital phase shifters 191-19N. is added or subtracted to/from the count till the result enters a preset range and the optimum absolute phase of antenna elements 211-21N, is obtained without changing the relative phase. Then the result is outputted to phase shifter drivers 171-17N. Thus, the power consumption of the phase shifter drivers enters a set range, thus the power consumption is averaged and the phase array antenna system whose power consumption is not zero is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a phased array antenna device that is mounted on one, for example, nine artificial satellites and forms a beam in an arbitrary direction on orbit.

[Prior Art] A phased array antenna uses a plurality of antenna elements called subarrays to form an equal phase plane that is perpendicular to a desired direction.

It is an antenna that forms a beam. Compared to mechanically operated antennas, beam switching can be achieved in a short time and with high precision. Furthermore, even if one antenna element system fails, it can be covered by the remaining antenna elements.
This is an antenna with extremely high reliability.

FIG. 2 is a configuration diagram of a conventional phased array antenna device.

In the figure, (1) is data on the direction of the beam to be formed, and (2) is a phase amount calculation circuit. The phase amount calculation circuit (2) includes a calculator, and the positions of N antenna elements and the frequencies to be used are inputted in advance.
Using the beam direction data (1) above, calculate the optimal phase amount for directing the beam in the desired direction with an accuracy of 9M bits for N antenna elements (21,j~+21.1, The M-bit phase amount (311 to (3N)) of (
It is output to a latch circuit (15) of N×M) bits. Further, the phase amount calculation circuit (2) converts the timing signal (4) for switching the beam direction data (1) into the (N
×M)-bit latch circuit (15), and the latch circuit (15) outputs N M-bit phase amounts (16+) to f16 at the timing of the timing signal (4).
．． l M-bit phaser driver (17,) ~ +17N)
Output to. The N M-bit phaser drivers (17
, j ~ (17, 1 is the total of M 9 transistor circuits (NXX how many transistor circuits), and the above N M bit phase amount (
The "ON" and "F" states of the transistors are determined by the "l" and "0" states of the respective bits 16,1 to (16N). The N M-bit phaser drivers (17
, j ~ (17N) transistor output (IL) ~ (18
Nl is the first to Nth M-bit digital phase shifter (1
9,) to (19,). As a digital phase shifter, a hybrid-coupled phase shifter using a PIN diode is commonly used for phased arrays, and the phase amount is set by applying a reverse bias or forward bias to this PIN diode. The first to Nth M-bit digital phase shifters (19,1 to (19
□), the phase amounts of the corresponding first to Nth antenna elements (21,) to (21,1) are determined, and the first to Nth antenna elements (21,1 to (21,1) are The beam of the phased array antenna is formed by generating nine equal phase planes in the directions indicated by the beam direction data (11).

[Problems to be Solved by the Invention] In the conventional phased array antenna device as shown in FIG. ~(1
7N) is larger than other parts, and its fluctuation is also large. This depends on the state of each output bit of the 1-phase amount calculation circuit (2).
) to (17N) is determined whether the corresponding transistor is "ON" or OFF", but the output bit of the 9 phase amount calculation circuit (2) changes irregularly depending on the beam direction data (1) inputted by 9. For example, when the output bit of the phase amount calculation circuit (2) is l'', the phase shifter driver (1
7,) to (17If the transistors in Nl are designed to be “ON”, the output of the phase amount calculation circuit (2) is outputted via the latch circuit (15), and its output (16,1 ~(16,), the larger the number of “l”, the more N M-bit phaser drivers (1711~(17,)
N)'s power consumption increases. Furthermore, depending on the input beam direction data, in the worst case, the power consumption of N M-bit phase shifter drivers (17,1 to (17N+) may become zero.

In a phased array antenna device on the ground, N M-bit phaser drivers (171) to (17N)
Problem 9 does not arise because a large-capacity constant voltage source that can sufficiently cope with fluctuations in power consumption can be prepared. Furthermore, since the number N of antenna elements is set sufficiently large, statistically, the variation in the number of bits that become "1" is small (and the power consumption is averaged out).

However, when this phased array antenna device is mounted on one artificial satellite, due to restrictions such as weight, only a smaller number of antenna elements can be prepared compared to the case on the ground, so the number of bits varies greatly depending on the beam direction. Furthermore, there was a problem in that it was extremely difficult to prepare a large-capacity power source that could withstand large load fluctuations like in the case of terrestrial systems. Also, N M-bit phaser drivers (17
, 1 to (17, 1) when the power consumption becomes zero.

There was a problem in that the secondary output of the conventional on-board power supply, the DC/DC converter, became overvoltage, causing the phased array antenna device to malfunction.

This invention has been made to solve such problems, and provides a phased array antenna device in which power consumption fluctuations of N M-bit phaser drivers are reduced without changing the beam direction, and power consumption does not become zero. The purpose is to

[Means for Solving the Problems] A phased array antenna device according to the present invention adds or subtracts the phase amount of the minimum unit of a digital phase shifter to each phase amount of each antenna element an appropriate number of times. By doing so, the absolute phase of each antenna element can be changed without changing the relative phase between the antenna elements.

[Operation] In the phased array antenna system according to the present invention, first, an adder counts the number of "1"s in the bit string of the M-bit phase amount of the N antenna elements, which is the output of the 1 phase amount calculation circuit, and until it falls within the set range.
By adding or subtracting the minimum unit phase amount of the digital phase shifter, the optimal absolute phase of each antenna element is determined without changing the relative phase. This value is then output to the phase shifter driver.

As a result, the power consumption of the single-phase shifter driver falls within the set range, thus making it possible to provide a phased array antenna device in which the power consumption is averaged and the power consumption does not become zero.

[Example] FIG. 1 is a block diagram showing an embodiment of the present invention.

In the figure, (1) to (3) and (15) to (21) are exactly the same as the conventional phased array antenna device described above. Also, (8□) to (shi) are phase amount calculation circuits
(2) outputs N M-bit phase amounts (3□) to (3
N) are respectively preset values, and the OR gate (6)
N M-bit up/down counters from the first to the Nth, which simultaneously count up or count down in synchronization with the clock (7) output from the (1
01 is the N bit up from the first to Nth above/
Outputs (9,) to (8,) of down counters (81) to (8,)
(121 is an output (13) that is output only when the output (11) of the above adder is within a preset range, and the above A magnitude comparator that outputs two outputs (14) that outputs only when the value is below the set range, (6) is a clock input from the outside (5)
is the output of the magnitude comparator (12) (13
) is an OR gate for masking.

In FIG. 1 above, for simplicity, M=4. The case where N=3 will be specifically explained.

The output of the phase amount calculation circuit (2) is (0111), (1
101).

(1111), the first to third 4 bits up/
Outputs (9,) to (83) of down counters (8,) to (83)
93).

(Gill), (1101), (11
11). Adder (lO) output +1
11 is lO''.Magnitude comparator (1
If the setting range of 2) is 4≦ and ≦8, then 'lO'' is outside the range and not below the range, so the output f13) of the magnitude comparator (12), (141
Therefore, the externally input clock (5) is outputted from the first to third 4-bit up/down counters (8□) as the output (7) of the OR gate (6).
) to (83). Furthermore, the output (14) when outside the range of the above magnitude comparator (12)
are also input to the first to third 4-bit up/down counters (81) to (83), and if the output (14) is "H", count up is selected, and if the output (14) is "L", count down is selected. Then, in this case, the first to third 4-bit up/down counters (8,) to (
83) selects countdown, and selects the first to third 4-bit up/down counters (s,) to (as).
The output (9,) ~ (9, 7 are each (01101
(1100), (11101. At this time, the output of the adder (10) (7) becomes '7'', which is within the setting range of the magnitude comparator (12), and the output when within the above range (13 ) becomes “H”. Therefore,
From this point on, the externally input clock (5) is
It is masked by the output (13) input to the OR gate (6) when it is within the above range, and is not output to the first to third 4-bit up/down counters (81) to (83). Therefore, the output (3,
) to (33), the first to third 4-bit up/down counters (8,) to (8,
3) outputs (9,) to (9N) do not change.

Furthermore, the output of the 9th-order phase amount calculation circuit (2).

Consider the case of (01001, (00101, +00001). At this time.

The output of the adder (10) is "2", which is outside the setting range of the magnitude converter 2) and below the range, so the output (13) is "L" when it is within the above range, and "L" when it is below the range. The output (14) becomes "H". Therefore, the output of the first to third 4-bit up/down counters (8,
) to (83) select the count up and its output (9
1) to (93) are finally (0101).

(0011), (0001).

In the above specific examples, in the case of the conventional example, the variation in power consumption was suppressed from "IO" to 2", whereas in one embodiment of the present invention, the variation in power consumption was suppressed to 7" to 5". .

As described above, the output of the 9 phase amount calculation circuit is obtained.

By adding or subtracting the phase amount, it is possible to reduce the fluctuation in the power consumption of the phase shifter driver without changing the relative phase completely, that is, without changing the beam direction.

[Effects of the Invention] As explained above, the present invention adds or subtracts an appropriate phase amount to the M-bit phase amount of the N antenna elements outputted by the 1 phase amount calculation circuit, thereby calculating the relative value of the N antenna elements. This has the effect of reducing fluctuations in power consumption of the nine-phase shifter driver without changing the phase. Therefore, there is an effect of realizing a phased array antenna device for use on a satellite in which it is difficult to prepare a large-capacity power source that can withstand large load fluctuations.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of an apparatus showing an embodiment of the present invention, and FIG.
The figure is a configuration diagram showing a conventional device. In the figure, (2) is a phase amount calculation circuit, (6) is a logical sum game (-, la, ) to (8,) is an M-bit up/down counter, (10) is an adder, and (12) is a magnitude Comparator, (15) is (N×M) bit latch circuit, (17,) to (17N) are M-bit phase shifter drivers, 11911 to (19,1 is M-bit digital phase shifter, (21,) to (21%) is the antenna element. Note that the same line numbers in the two figures indicate the same or equivalent parts.

Claims (1)

[Claims] a phase amount calculation circuit that receives the beam direction to be formed;
N (N is any positive integer) M numbers from the first to the Nth, each having the output of the phase amount calculation circuit as a preset value.
(M is any positive integer) The bit up/down counter and the outputs of the N M-bit up/down counters are input, and the output is switched according to the timing signal from the phase amount calculation circuit (N×M). a latch circuit, N M-bit phase shifter drivers from the first to Nth whose inputs are the outputs of the (N×M) bit latch circuits, and the outputs of the N M-bit phase shifter drivers. N M-bit digital phase shifters from the first to Nth input, and N M-bit digital phase shifters from the first to Nth whose phase amounts are respectively set by the above-mentioned N M-bit digital phase shifters. A phased array antenna having an antenna element as a component, an adder for counting the total number of "1"s among the (N×M) bits that are the outputs of the N M-bit up/down counters, and the adder. Equipped with a magnitude comparator that outputs a predetermined level when the output is within a preset range and when it is below the range, and an OR gate that receives an externally input clock signal and the output of the magnitude comparator as input. A phased array antenna device featuring: