JPH0454720A - Serial pn pattern parallel generating circuit and constitution method for the circuit - Google Patents

Abstract

(57) [Abstract] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] Regarding a series PN pattern parallel generation circuit that generates series PN patterns (pseudorandom patterns) in parallel, a series PN pattern of an arbitrary order can be generated with an arbitrary width larger than the order of the PN pattern. The purpose is to configure it so that it can be output in parallel with p, n, and m such that p>n>
When m is a satisfying natural number, the first stage is an exclusive OR of an n-stage shift register consisting of n registers, the register output of the final stage in the shift register, and the register output of the m-th stage. an n-th order feedback shift register circuit comprising an EOR circuit that applies voltage to the registers of p−n; Naru p
- a p-dimensional number vector consisting of the input values of each of the p registers in a p-stage feedback shift register composed of n-stage shift registers, and the output value of each of the p registers; A p-dimensional number vector consisting of the input value of each of the p registers, and each of the p registers, by a square matrix that is the p-th power of a pXp-dimensional square matrix that expresses the relationship with the p-dimensional number vector. a p-stage shift register in which the input and output of each register are connected to each other such that the relationship with a p-dimensional number vector consisting of output values is shown by the p-th power square matrix; E that realizes the connection relationship shown by the matrix
It is configured to include an OR circuit.

[Industrial application field]

The present invention uses a serial PN pattern (pseudorandom pattern)
This invention relates to a series PN pattern parallel generation circuit that generates PN patterns in parallel.

In order to generate a serial PN pattern (pseudo-random pattern), an M-sequence generation circuit with a period of 2"-1 based on an n-th order generator polynomial is used, but in order to generate a 20 PN pattern serially, In this case, the generating circuit must also operate at a bit rate equal to this serial output, which may be difficult to implement or require the use of a circuit configuration that consumes a large amount of power in order to operate at high speed.

Therefore, the technique is to generate a parallel pattern that is equal to a predetermined length of a serial PN pattern by performing parallel/serial conversion, and then to obtain the desired serial pattern by performing parallel/serial conversion on this parallel pattern. It has been known. Thereby, the operating speed of the pseudo-random pattern generation circuit can be slowed down by a multiple equal to the width of the parallel pattern.

Such a series PN pattern (pseudorandom pattern)
It is desired that a series PN pattern parallel generation circuit that generates PN patterns in parallel can be configured to output a PN pattern of any order with any width depending on the purpose of use.

[Prior art and problems to be solved by the invention] In the conventional technology, the first method of configuring a series PN pattern parallel generation circuit that generates series PN patterns (pseudorandom patterns) in parallel is to (Parallelism degree) This is used only when p satisfies p = = 2k, and when the degree of the generator polynomial is n, it is used when the phase of the serial pattern is shifted by 2''/p bits. This is done by providing the series in parallel.

The second method is used only when p≦n (p is less than or equal to n), and is based on an n-th order generator polynomial.
Data input d of n flip-flop circuits constituting the 10M sequence generation circuit, number vector d whose elements are (i=1 to n), and data outputs qi of each (i=1 to n)
Ap is calculated based on the n-th order square matrix A whose relationship with a number vector q whose elements are d = Aq, and each data input d, (i = 1 to n) is an element. The relationship between the number vector d and the number vector q whose elements are each data output qz (]-1 to n) constitutes a circuit expressed as d=APq, and n flip-flops constituting this circuit. This is done by taking out the outputs of arbitrary consecutive p flip-flop circuits in the circuit in parallel.

However, depending on the first and second methods described above, in the case of p=2 and the case of p≦n, a serial PN pattern (pseudo-random pattern) is created.
It is possible to construct a series PN pattern parallel generation circuit that generates in parallel p, but it is not possible to construct a series PN pattern parallel generation circuit that generates series PN patterns (pseudo-random patterns) in parallel for any other p. The problem was that I couldn't do it.

The present invention has been made in view of the above problems, and is a series PN pattern that can be configured to output a series PN pattern of any order in parallel with an arbitrary width larger than the order of the PN pattern. It is an object of the present invention to provide a PN pattern parallel generation circuit and a method of configuring the series PN pattern parallel generation circuit.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic procedure of a method for configuring a series PN pattern parallel generation circuit according to the present invention.

In Figure 1, (1) represents p, n and m as p〉
When n is a natural number satisfying n>m, the exclusive OR of an n-stage shift register consisting of n registers, and the register output of the final stage and the register output of the m-th stage in the shift register is expressed as An n-th feedback shift register circuit having an EOR circuit applied to the first stage register, and p-n registers connected in series to the output of the last stage register of the n stage shift registers. The first step [2) of configuring a p-stage feedback shift register consisting of a p-n stage shift register consisting of a p-dimensional number vector consisting of input values,
The second step is to obtain a pXp-dimensional square matrix that expresses the relationship between the output values of each of the p registers and the p-dimensional number vector. (3) The square matrix is raised to the pth power. The third step is to obtain a square matrix, and (4) is p consisting of the input values of each of p registers.
The input and output of each register are connected to each other so that the relationship between the p-dimensional number vector and the p-dimensional number vector consisting of the output value of each of the p registers is shown by the square matrix raised to the p power. This is step 4.

In addition, in the present invention, in the calculation of the above-mentioned matrix and number vector, addition is performed using exclusive OR.

[For production]

FIG. 2 shows an example of an M-sequence generation circuit with a period of 2h-1 based on an n-th order generator polynomial, with a period of 2''' based on an n-th order generator polynomial X''+X'+1.
This figure shows the configuration of the M-sequence generation circuit (feedback type shift register circuit) of -1. In Figure 2, 11+1
2+...l ,,-2+ 1h-1+ lh is,
Each is a latch circuit (register), and 2 is an EO
This is an R circuit, and in each latch circuit, d indicates a data input terminal, and q indicates an output terminal.

Based on the generator polynomial X''+X'+11:, the EOR circuit 2 calculates the exclusive OR of the output q of the n-1st stage latch circuit 1., -1 and the output q of the nth stage latch circuit 1. The signal is calculated and applied to the data input d of the first stage latch circuit 11.

FIG. 3 shows a p-n latch circuit (register) consisting of p-n latch circuits (registers) connected in series to the output of the final stage register of the n-stage feedback shift register circuit according to the second step 2 of the present invention. This figure shows the configuration of a p-stage feedback shift register circuit formed by connecting stages of shift registers. Third
In the figure, 1. 11 1n+2+...1 p-
2+I P-1+I P are pn latch circuits that constitute the above pn stage shift register, respectively.

FIGS. 4A and 4B respectively show p-n registers connected in series to the output of the final stage register of an n-stage feedback shift register circuit, an example of which is shown in FIG. 3. p registers 11 constituting a p-stage feedback shift register circuit formed by connecting n-stage shift registers.
12. ...1□-2゜11. -1+10,1□1,1
．． . 2. . . . A number vector whose elements are the input values of I P-2+ I P-1+IP, and the p registers 1. ．． 1□,...1,,-2+ 1 h-II1
,．． 1. ,ya11 11'l+2+...1 p-L
1p-1+ shows two methods of expressing a square matrix showing a relationship with a number vector whose elements are the respective output values of IP.

FIG. 4A shows p registers 10.1□, . . . L-211, -, configuring a p-stage feedback shift register circuit.
,1ゎ+ III+ 11%+2+...I
P-2+I P-1n1, each input value is di,
d2. ...dn.

...dp, and the p registers 11+ 12+.
・1 fi-211n-II 1h l 1ft+
ll In+2+...1 p-2, 1p-+, 1
Each of p (D$ output as Ql, Q2゜...qn,...
- As qp, these input values di, d2 . ...
How to express a square matrix that shows the relationship between a number vector whose elements are dn, ...dp, and a number vector whose elements are these output values ql, q2゜...qn, ...qp It shows.

Further, FIG. 4B shows p registers I II 12+...1 constituting a p-stage feedback shift register circuit.
h-2+ L-1n ITh + lh. l+
1 h+2+...1p-2+1□ Each input value of 1, 1F is dp,...dn.

...d2. di, and the p registers 1. .

12,...1 h-2+ In-1+ In +
111+l+ 1n+2+...I P-2+
Each output value of I P-1+ I P is qp.

...qn, ...q2. ql, these input values dl, d2 . ...dn, ...dp as elements, and their output values q1゜q2.・・・
This shows a method of expressing a square matrix showing the relationship with a number vector q whose elements are qn, . . . qp.

In the representation method of Figure 4A, the Kamikita square matrix is n
Period 2, based on the following generator polynomial Xh+X"-"+1
″-1 M-sequence generation circuit (feedback shift register circuit)
In , 1≦l≦p, the output q1 of the first stage register is applied as the input di+1 of the i+1th stage register, so they are equal to each other, and the output of the mth register and the nth register Since the exclusive OR with the output of is applied as the input of the first stage register, α is α=
(0,...0. 1. 0....0.1.0...
・It is expressed as 0). Here, "1" means 1 row n
- an element in column m and an element in row 1 and column n.

For example, in the case of an M-sequence generation circuit (feedback shift register circuit) with a period of 2fl-1 based on the generator polynomial X''+X' +1, α is α=(0,...0°1.1.0.
...0). Here, "1" is the element in the 1st row, column n-1, and the element in the 1st row, column n.

In the representation method of FIG. 4B, the above square matrix is n
Period 2, based on the following generator polynomial Xh+X″−”+1
″-1 M-sequence generation circuit (feedback shift register circuit)
In , 1≦1≦p, the output qi of the first stage register is applied as the input d1-1 of the 1-1st stage register, so they are equal to each other, and the output of the mth register and n Since the exclusive OR with the output of the register in the first stage is applied as the input to the register in the first stage, β becomes β=
(0,...0.1.0....0.1.0...
・It is expressed as 0). Here, "1" is p row p
- an element in column m and an element in row p and column p-n+1. For example, based on the generator polynomial x''+x'+1, the period 2h-
In the case of a No. 1 M-sequence generation circuit (feedback shift register circuit), β is β=(0°...0. 1. 1. 0...
0). Here, "1" is p-row p-
An element in column 1 and an element in row p and column p-n+1.

Also, the number vector d in the t-th cycle of the clock
(t) and the number vector q (t+1) at the t-1th cycle of the clock, q(t+1)=d (t
), and between the number vector q(t) in the t-th cycle of the clock and the number vector q(t-1) in the t-1th cycle of the clock, q(t)=AQ
Since there is a relationship of (t-1), q (t) = Atq
The relationship (0) holds true. Here, if we set B = AP and r (t)"Q (pat), then r (
t)=Btr (0)=A”tq (0)=q (p
at), so not only q(1) but also r(t)
is also on the generation sequence of the circuit of FIG. And r (t
+1) = q(p*(t+1)) is also on the generation sequence of the circuit of FIG.
+1))=Br (t)= (A')q (pat)
Therefore, r (t+1)=q (p* (t+1)
) has undergone p time slot transitions on its generation sequence for each element of r (t)=q (pat). Here, in the representation method of FIG. 4A, since the p-th element rp(t) of the number vector r (t) has transitioned from the first element 1(t) to p time slots, the number vector r The pth element rp of (t) (t) is the first element r of the next cycle number vector r (t+1)
It is continuous on the generation sequence to l (t+1). Therefore, let p elements of the number vector r(t) be rl(t)
By multiplexing (parallel-serial conversion) in the direction of →rp (t), the original generation sequence can be obtained.

Similarly, in the representation method of FIG. 4B, the number vector r
If p elements of (t) are multiplexed (parallel-serial conversion) in the direction rp (t)→r1(1), the original generation sequence can be obtained.

〔Example〕

As an embodiment of the present invention, a procedure for configuring a series PN pattern parallel generation circuit when the degree of the generator polynomial is n = 7 and the degree of parallelism p = 9, and a series PN pattern parallel generation circuit configured by the procedure. The configuration is shown below.

First, according to the first and second steps of the present invention described above, as shown in FIG. ), consider a configuration in which 9-7=2 stages of shift registers are connected in series.

Then, according to the third step of the present invention described above, a fifth step is performed.
Each register in the configuration shown in the figure (flip-flop circuit FFI~
FF9) input values dl, d2゜...dn, ...d
A number vector with p as an element and these output values Q1. Q
2. The relationship between . . . qn, .

Next, according to the fourth step of the present invention described above, as shown in FIG.
P is calculated, and further, using this matrix, input values d1, d2, . ...dn,
...dp is the output value q1 of each register. q2.
...qnr ...qp can be expressed.

FIG. 8 shows the configuration of a series PN pattern parallel generation circuit having the input/output relationship shown in FIG.

In FIG. 8, the first stage flip-flop circuit FF
The exclusive OR of the output q4 of the fourth stage flip-flop circuit FF4 and the output d6 of the sixth stage flip-flop circuit FF6 is applied to the input d1 of I from the EOR circuit 27. An exclusive logic between the output q5 of the fifth flip-flop circuit FF5 and the output d7 of the seventh flip-flop circuit FF7 is input from the EOR circuit 28 to the input d2 of the second flip-flop circuit FF2. The sum is applied. In the EOR circuit 29, the exclusive OR of the output q6 of the sixth stage flip-flop circuit FF6 and the output d6 of the sixth stage flip-flop circuit FF6 is calculated, and further, in the EO,R circuit 26, the EOR circuit 2
9 and the output q1 of the first stage flip-flop circuit FFI is calculated and applied to the input d3 of the third stage flip-flop circuit FF3. Fourth
The input d4 of the flip-flop circuit FF4 of the stage is E.
From the OR circuit 21, the first stage flip-flop circuit F
FI output q1 and second stage flip-flop circuit FF
The exclusive OR with the output d2 of 2 is applied. The input d5 of the fifth stage flip-flop circuit FF5 has EOR
From the circuit 22, the second stage flip-flop circuit FF2
The exclusive OR of the output q2 of and the output d3 of the third stage flip-flop circuit FF3 is applied. The exclusive logic between the output q3 of the third stage flip-flop circuit FF3 and the output d4 of the fourth stage flip-flop circuit FF4 is input from the EOR circuit 23 to the input d6 of the sixth stage flip-flop circuit FF6. The sum is applied. An EOR circuit 24 is connected to the input d7 of the seventh stage flip-flop circuit FF7.
, the output q of the fourth stage flip-flop circuit FF4
4 and the output d5 of the fifth stage flip-flop circuit FF5
The exclusive OR with is applied. An exclusive logic between the output q5 of the fifth stage flip-flop circuit FF5 and the output d6 of the sixth stage flip-flop circuit FF6 is input from the EOR circuit 25 to the input d8 of the eighth stage flip-flop circuit FF8. The sum is applied. The input d9 of the ninth stage flip-flop circuit FF9 is supplied with the output q6 of the sixth stage flip-flop circuit FF6 and the seventh stage flip-flop circuit FF6 from the EOR circuit 29.
An exclusive OR with the output d7 of the flip-flop circuit FF7 in the second stage is applied. In this way, the outputs q1 to q of the nine flip-flop circuits FFI to FF9 in the circuit of FIG.
9, the parallel outputs r1 to r9 of the target PN pattern are obtained. By multiplexing these parallel outputs in the order of r1→r9, an n-th order serial PN pattern having a period of 2''-1 is obtained.

FIG. 9 shows an example of application of the series PN pattern parallel generation circuit shown in FIG. FIG. 9 shows parallel input data di, d2. with a degree of parallelism of 9. . . d9 is multiplexed and transmitted serially, instead of scrambling the serial data with a serial PN pattern, the parallel input data d1. d2. ...
d9 by the parallel outputs r1 to r9 of the circuit in FIG.
Scramble each (take exclusive OR). As mentioned above, the parallel outputs r1 to r9 of the circuit shown in FIG. Parallel input data dl, d2.
. . d9 is multiplexed in the multiplexing circuit after the above-mentioned scrambling, so that the same serial data as serial data scrambled with a serial PN pattern can be obtained with the configuration shown in FIG.

〔Effect of the invention〕

According to the series PN pattern parallel generation circuit of the present invention, it is possible to output serial PN patterns of any order in parallel with any width greater than the order of the PN patterns.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic procedure for configuring a serial PN pattern parallel generation circuit according to the present invention, FIG. 2 is a diagram showing the configuration of an n-stage feedback shift register circuit, and FIG. 3 is a diagram showing the configuration of an n-stage feedback shift register circuit. p consisting of p-n registers in series with the output of the final stage register of the feedback shift register circuit.
- Figures 4A and 4B are diagrams showing the configuration of a p-stage feedback shift register circuit formed by connecting n-stage shift registers. p registers constituting a p-stage feedback shift register circuit formed by connecting a p-n stage shift register consisting of p-n registers in series to the output of the final stage register of the feedback shift register circuit. Figure 5 is a diagram showing two methods of expressing a square matrix showing the relationship between a number vector whose elements are the input values of each of the p registers and a number vector whose elements are the output values of each of the p registers. , 9-7=2 for an M-sequence generation circuit (feedback shift register circuit) with a period of 2''-1 based on the generator polynomial X''+X' +1
A diagram showing a configuration in which stage shift registers are connected in series.
d2. ...dn, ...dp as elements and their output values Q1. Q2゜...qn,
... A diagram showing the relationship between qp and a number vector q whose elements are: Figure 7 is a matrix A' that is the square matrix A of Figure 6 raised to the pth power;
i6, and further, the input values di, d2, ... dn to each register of the target circuit obtained by matrix A'
, . . . Output values of each register of dp ql, q2 .
. . . qn, . . . qp. . . . FIG. 3 is a diagram showing an application example of the series PN pattern parallel generation circuit shown in the figure. [Explanation of symbols] FFI~F F 9. ,,-Flip-flop circuit, 2
0 to 29802 circuits, 30 series PN pattern parallel generation circuit, 50- multiplexing circuit. Square matrix A showing the relationship with the number vector q consisting of the first output values
Figure 6 shows the relationship between a number vector whose elements are input values of each register in Figure 5 and a number vector whose elements are output values.

Claims (1)

[Claims] When 1, p, n, and m are natural numbers satisfying p>n>m, an n-stage shift register consisting of n registers, and a register output of the final stage in the shift register; an n-th feedback shift register circuit comprising an EOR circuit that applies an exclusive OR with the m-th register output to the first-stage register; and a final feedback shift register circuit of the n-stage shift register. Consists of the input values of each of p registers in a p-stage feedback shift register, which is connected in series to the output of a stage register and is composed of a p-n stage shift register consisting of p-n registers. a p-dimensional number vector,
Let p be a p×p-dimensional square matrix that expresses the relationship between the output values of each of the p registers and a p-dimensional number vector.
The relationship between the p-dimensional number vector consisting of the input values of each of the p registers and the p-dimensional number vector consisting of the output values of each of the p registers is determined by the p-th power square matrix. A p-stage shift register in which the inputs and outputs of each register are connected to each other as shown by the square matrix, and an EOR circuit that realizes the connection relationship shown by the square matrix raised to the p power. Characteristic series PN pattern parallel generation circuit. 2. When calculating the square matrix and the number vector, addition is performed by exclusive OR, and the connection corresponding to the addition is EO
2. The series PN pattern parallel generation circuit according to claim 1, which is implemented by an R circuit. 3. The number vector consisting of the input values is configured with the input values of each of the p registers as elements corresponding to the order or reverse order of data flow in the p-stage feedback shift register, A number vector consisting of the output values is set in the p-stage corresponding to the order or reverse order of the data flow in the p-stage feedback shift register.
2. The serial PN pattern parallel generation circuit according to claim 1, wherein the serial PN pattern parallel generation circuit is constructed by using the output values of each of the registers as elements. 4. When p, n, and m are natural numbers satisfying p>n>m, there is an n-stage shift register consisting of n registers, the register output of the final stage in the shift register, and the m-th stage register. an n-th feedback shift register circuit comprising an EOR circuit that applies an exclusive OR with the output to the first stage register, and an output of the final stage register of the n stage shift register; a first step (1) constituting a p-stage feedback shift register composed of p-n stage shift registers connected in series and consisting of p-n registers; and the p-stage feedback shift register. A p×p-dimensional number vector representing the relationship between a p-dimensional number vector consisting of the input values of each of the p registers in the register and a p-dimensional number vector consisting of the output values of each of the p registers. a second step (2) for obtaining a square matrix; a third step (3) for obtaining a square matrix that is the square matrix raised to the p power; and a p-dimensional number vector consisting of the input values of each of the p registers. and a p-dimensional number vector consisting of the output value of each of the p registers is shown by the square matrix raised to the p power, a fourth step of connecting the input and output of each register ( 4) A method for configuring a series PN pattern parallel generation circuit, comprising: 5. When calculating the square matrix and the number vector, addition is performed by exclusive OR, and the connection corresponding to the addition is EO
5. The method of configuring a series PN pattern parallel generation circuit according to claim 4, wherein the method is performed using an R circuit. 6. The number vector consisting of the input values is configured with the input values of each of the p registers as elements corresponding to the order or reverse order of data flow in the p-stage feedback shift register, The number vector consisting of the output values is configured with the output values of each of the p registers as elements corresponding to the order or reverse order of the data flow in the p-stage feedback shift register. The series PN pattern parallel generation circuit according to item 4.