JPH0454982B2 - - Google Patents

Description

[Detailed Description of the Invention] (1) Technical Field of the Invention The present invention relates to a high voltage resistance element comprising an impurity diffusion layer provided on a semiconductor substrate, and particularly relates to a high voltage resistance element that can be formed in a fine pattern within an integrated circuit. Regarding elements.

(2) Background of the technology Various resistance elements have been proposed in the past in which an impurity diffusion layer is formed on a semiconductor substrate to form a low resistance element, but the resistance value generally has an error of about ±20%.
Those with a resistance of about 10Ω to 30KΩ are used.

Generally, interrupt type resistors are used to obtain high resistance. In other words, a high resistance value was obtained by creating an n ⁺ emitter diffusion layer in the P-type base diffusion layer, reducing the thickness of the base diffusion layer, and superimposing the emitter diffusion layer on most of the highly concentrated base diffusion layer. Although this type of resistor is known, it has drawbacks such as large errors in resistance values during each manufacturing process.

In addition to such resistance elements, MOS resistances are also known. These require a large area
A MOS resistor is used as a load resistor.For example, as a MOS load resistor, the gate and drain of MOSFET are
An electrode short-circuited is used. A general MOS type resistance element structure will be explained below.

(3) Prior art and problems Figure 1 is a cross-sectional view of a conventional MOS resistor, and Figure 2 is a cross-sectional view of a resistor in which a conventional high-concentration impurity diffusion layer is formed on a substrate, as previously proposed by the applicant. It is.

In FIG. 1, reference numeral 1 denotes an n-type substrate made of, for example, silicon, on which a field oxide film 2 and an oxide film 3 are formed, and a p ⁺ impurity high concentration diffusion region 4 is formed below the oxide film 3.

Electrode windows 5a and 5b are formed on the oxide film 3, and an insulating layer 6 such as PSG (phosphorus silica glass) is formed on the oxide film 3 and the field oxide film 2.
Electrodes 7a and 7b made of Al are patterned on a and 5b to form a resistance element between the electrodes 7a and 7b.

Figure 2 shows a resistance element proposed by the applicant.
At the lower ends of the electrode windows 5a and 5b corresponding to the drain and source of the MOSFET, there are p ⁺ impurity high concentration diffusion regions 8 and 10, and a p ^- impurity low concentration diffusion region 9 is provided between the high impurity concentration diffusion regions. The dose amount of the low impurity concentration diffusion region 9 is 10 ¹² ~
10 ¹³ Atom/cm ² and high impurity concentration diffusion region 8,
The dose of 10 is 10 ¹⁵ Atom/cm ² degrees. In addition,
A channel stopper 11 is in contact with the high impurity concentration diffusion regions 8 and 10. Since the other configurations are the same as those in FIG. 1, repeated explanation will be omitted. Such a configuration has the disadvantage that a resistive element with high breakdown voltage cannot be obtained. Currently, a display circuit as shown in FIG. 3 is used as a high-voltage integrated circuit to drive a high-voltage device such as a fluorescent display tube, and a high-voltage resistor 17 is used in such a circuit. . That is, the third
In the figure, the integrated circuit section includes P-MOS 13 and N-MOS 1.
A complementary MOS inverter composed of 4 and an output drive transistor made of, for example, P-MOS, which serves as a drive section, is composed of a high-voltage element 15, and the light is transmitted through a pad 16 connected to the high-voltage element. An "on" and "off" voltage is supplied to the grid G of the light display tube 20 to cause the fluorescent display tube to blink.

The cathode C of the fluorescent display tube 20 is connected to a voltage source 18 of, for example, about -35V through a Zener 19.
A voltage of about 30V is applied, and a high voltage resistor 17 of about 100KΩ is connected between the voltage source 18 and the grid G to prevent flickering during blinking.
Since such a high voltage resistor 17 is externally attached to each fluorescent display tube, the cost is lower than the resistor 1.
However, in a system having a large number of fluorescent display tubes, the mounting area increases, which is a big problem in making the system more compact.

(4) Object of the Invention In view of the above-mentioned conventional drawbacks, the first object of the present invention is to integrate a high resistance element comprising an impurity diffusion layer in a high voltage integrated circuit. A second object of the present invention is to integrate a high voltage resistance element into a semiconductor device.

A third object of the present invention is to provide a high-voltage resistance element that has a breakdown voltage of -40V or more within an extremely small area (W/L=about 10μ/100μ).

Still another object of the present invention is to provide a method of manufacturing a high voltage resistance element as well as a high voltage resistance element such as a high voltage transistor or a high voltage protection element.

(5) Structure of the Invention According to the present invention, this object is to provide two spaced apart conductivity types opposite to the semiconductor substrate in an active region separated by a thick insulating film of a semiconductor substrate at a position spaced apart from the thick insulating film. A high impurity concentration region is formed between the two high impurity concentration regions and around the entire periphery of the high impurity concentration regions and in contact with the two high impurity concentration regions to have the same conductivity as the high impurity concentration regions. Achieved by a semiconductor device characterized in that it includes a high breakdown voltage resistance element formed by forming a low impurity concentration region of the same type as the semiconductor substrate and a channel stopper region of the same conductivity type as the semiconductor substrate under the thick insulating film. be done.

(6) Embodiment of the Invention An embodiment of the present invention will be described below with reference to FIGS. 4 to 9.

FIGS. 4a and 4b are a sectional view and a plan view of a high voltage resistance element according to the present invention, and FIGS. 5a and 5b are a sectional view and a plan view of a high voltage resistance element according to another embodiment of the invention. In the case of FIGS. 4a and 4b, the impurity dopant of the same conductivity type is implanted with the same dose or a different dose as that of the low impurity concentration diffusion region 9 formed between the two high impurity concentration diffusion regions 8 and 10. Concentration diffusion region 21
As is clear from the plan view of FIG. 4b, it is formed so as to surround the two high impurity concentration diffusion regions 8 and 10 and the low impurity concentration diffusion region 9, and a channel at the lower end of the field oxide film 2, which is a thick insulating film. Stoppa 11
This is the case where there is a gap 22 between the low impurity concentration diffusion region 21, and the case shown in FIGS. 5a and 5b is the case where the low impurity concentration diffusion region 21 and the channel stopper are in contact with each other. In the case of FIG. 4, a high voltage resistor can be obtained. Although the withstand voltage in FIG. 5 is slightly lower than that in FIG. 4, it is much higher than that in the case in which the channel stopper 11 collides with the high impurity concentration diffusion regions 8 and 10 proposed by the applicant in FIG. Pressure resistance improves.

A diffusion region is formed in the semiconductor substrate as described above, and instead of the external resistor 17, a high voltage resistance element 17' is used as shown by the dotted line, and a high voltage resistance element 15 is installed in the integrated circuit 12 as shown in FIG. The process of simultaneously forming on the substrate will be described in detail with reference to FIG. In addition, in FIG. 6, the process of simultaneously manufacturing the high voltage resistance element 15 on the left side and the high voltage resistance element 17' on the right side is shown.

In FIG. 6a, the substrate 1 is made of silicon with a concentration of 5
×10 ¹⁵ cm ^-3 n-type, and there is an oxide film 4 on the substrate 1.
4 (SiO ₂ ) to a thickness of 500 Å, a nitride film 23 (Si ₃ N ₄ ) is formed to a thickness of 1000 Å on the insulating film 44 made of SiO ₂ .
The nitride film 23 is formed thickly and is exposed to light using a mask that defines an active region to form the nitride film 23 as shown in FIG.
Selective etching as in

Figure 6b shows resist 25 for channel cutting.
is applied onto the nitride film 23 and the insulating film 44 and patterned with a mask to form a window, and then the window opening portion 2 is formed.
From step 6, ions of phosphorus (P) are implanted 27. The channel stopper region 11 is formed in the substrate 1 by implanting at a dose of 6×10 ¹² cm ⁻² and 80 KeV.

Next, the resist film 25 is removed and a field oxide film, that is, a thick insulating film 2, which is thermally oxidized using the nitride film 23 as a mask, is formed. (FIG. 6c) Here, the nitride film 23 and the oxide film 44 formed under the nitride film 23 are removed.

Next, as shown in FIG. 6d, a gate oxide film 30 is formed between the thick insulating films 2, 2. The thickness of the gate oxide film 30 is about 700 Å.

A threshold control layer 31 is formed by implanting boron (B ⁺ ) of approximately 10 ¹¹ cm ^-2 by ion implantation 29 onto the gate oxide film 30 of the high-voltage device 15 shown on the left side of FIG. 6d. Ru. A layer on the thick insulating film 2 is a resist layer 28.

High voltage resistance element 17' shown on the right side of FIG. 6d
Threshold control layer 3 as required
Even if gate oxide film 3 is formed, there is no particular problem since the impurity dose is on the order of 10 ¹¹ cm ^-2 .
A resist layer 28 may be formed on the entire surface of the thick insulating film 2 and the boron implantation may not be performed.

Next, as shown in FIG. 6e, the resist layer 28 is removed, and the gate 32 of the high voltage element 15 is formed by coating and patterning polysilicon on the gate oxide film 30 as shown on the left.

Next, on the high voltage element 15 side, the gate oxide film 30 in the active region is removed, leaving only the gate oxide film 30 under the polysilicon gate 32. At this time, the gate oxide film 30 on the high voltage resistance element 17' side is also removed. Then, as shown in FIG. 6f, a new oxide film 3 is added.
3 is formed to a thickness of about 500 Å, a resist layer 34 is applied, and patterning is performed to remove the source 36 and drain 37 regions at a dose of 10 ¹⁵ cm ^-2
35 boron ions are implanted.

On the high voltage resistance element 17' side, a resist layer 34 is formed for patterning to form high impurity concentration diffusion regions 8 and 10, and a resist layer 34 is formed with 10 ¹⁵ cm of boron.
Ion implantation 35 is performed at a dose of ^-2 .

Next, as shown in FIG. 6g, after removing the resist layer 34, the high voltage resistance element 15 is also
7', boron with a dose of 10 ¹² cm ^-2 is diffused over the entire surface by ion implantation 38 to form a low impurity concentration diffusion region 39 around the drain region 37 of the high breakdown voltage element 15.
form.

As shown on the right side of FIG.
Diffuse 1.

Next, as shown in FIG. 6h, the resist 40 is completely covered on the high voltage resistance element 15 side, and the high voltage resistance element 17'
On the other hand, the resist 40 is patterned to remove only the upper surface of the low impurity concentration diffusion region 9, and boron ions are implanted 41.

The dose of the impurity at this time is changed depending on the resistance value to be obtained; at about 100KΩ, it is on the order of 10 ¹² cm ^-2 , and if you want to obtain a lower resistance value, increase the dose. The boron diffused between the two high impurity concentration diffusion regions 8 and 10 is often formed into a diffusion region having a conductivity type of p ₁ ⁻ +p ₂ ⁻ by overlapping.

In the above embodiment, in order to obtain a high breakdown voltage element 17', the impurity concentration between the two high impurity concentration diffusion regions 8 and 10 is reduced by overlapping ion implantation with different doses in FIGS. 6g and 6h. Diffusion dose amount of concentration diffusion region 9 and high impurity concentration diffusion regions 8 and 10
Although the diffusion dose of the low concentration impurity diffusion region 21 between the thick insulation layer and the thick insulating layer was made different, it is also possible to omit the step in FIG. be.

Furthermore, as shown in FIG. 7, after patterning a resist 41 between two high impurity concentration diffusion regions 8 and 10, boron ions are implanted at a dose of about 10 ¹² cm ^-2 , and then the resist 41 is removed and impurity Impurity diffusion may be performed at a dose smaller than that of the low concentration diffusion region 21.

The resist layer 40 is removed from the state shown in FIG. 6h, and PSG 6 is formed on the thick oxide film 2 and the oxide film 33 by CVD or the like as shown in FIG. 6i. Next, high voltage element 1
In step 5, holes are made for electrode windows for the source, drain, and gate, and on the other hand, in the high voltage resistance element 17', windows are made in the two high impurity concentration diffusion regions 8 and 10. Next, in order to suppress out-diffusion of phosphorus from the PSG film 6, a thin oxide film is grown. Next, the source/drain diffusion region 3 of the high voltage element 15 section
6, 37 and the high concentration diffusion regions 8, 10 of the high voltage resistance element 17' section, heat treatment is performed to control the depth of the diffusion layer, and the thin oxide film formed on the electrode window section is removed by etching the entire surface. After that,
The Al electrodes 7a, 7b, 7c are patterned to form a high breakdown voltage element, and the Al electrodes 7a, 7b are patterned to form high impurity concentration diffusion regions 8, 1.
A high withstand voltage resistance element is configured between 0 and 0.

The high breakdown voltage resistance element shown in FIGS. 4a and 4b is constructed through the manufacturing process as described above. Figure 5 a, b
The steps for obtaining a high breakdown voltage resistance element in the case where the channel cut 11 collides with the low impurity concentration diffusion region 21 shown in FIG. 6A are shown in FIG. Phosphorus is ion-implanted 27 using the patterned nitride film 23 as a mask without providing a resist layer as in the process described above. In this case, the dose is 6×10 ¹² cm ⁻² and the implant voltage is 80 KeV. Next, using the nitride film 23 as a mask, a field oxide film, that is, a thick insulating film, is formed by thermal oxidation, and the n ⁺ region 11 of the channel stopper is formed in the sixth region.
Unlike the diagram on the right side of FIG. c, the lower side of the thick insulating film 2 is covered.

The subsequent steps are exactly the same as in the process diagrams shown in FIGS. 6d to 6h, except that the channel stopper 11 portion covers the lower surface of the thick insulating film 2, and is shown in FIG. 6h.
A high voltage resistance element having the structure shown in FIG. 5a is obtained through the process.

In the above embodiment, the case where the high withstand voltage element 15 and the high withstand voltage resistance element 17' are formed on an N-type conductivity type substrate has been described, but as shown in FIGS. ', an n-type well is made in a p-type conductivity type substrate, and a p-type source/drain region or a low and high concentration diffusion region is formed in the well, or a p-type well is made in an n-type substrate and a p-type well is formed in the well. An n-type source and drain region or a low and high concentration diffusion region may be formed in the region.

FIG. 9 describes the manufacturing process of a high breakdown voltage element and a high breakdown voltage resistance element in which an N type well is formed in a p type substrate to form a p type low concentration or high concentration region.

FIG. 9 shows a process for simultaneously manufacturing a high voltage resistance element 15a on the left side and a high voltage resistance element 17a' on the right side.

In FIG. 9a, the substrate 1 is p-type 20Ωcm silicon, and an oxide film 44 (SiO ₂ ) is formed on the substrate.
After forming a 500 Å thick nitride film 23 on the SiO ₂
(Si ₃ N ₄ ) is formed to a thickness of 1000 Å and the nitride film 23 is patterned using a mask to define the active region, so that only the nitride film 23 below the resist film 24 is left. Next, as shown in Fig. 9b, window opening is performed and phosphorus (P ⁺ ) is added at a dose of 4× to form an n-well.
Ion implantation 42 was performed at 10 ¹² cm ^-2 and 250 KeV,
Next, running is performed for about 360 minutes in an N ₂ atmosphere at 1200° C. to form an n-type well 43 in the p-type substrate.

Next, as shown in FIG. 9c, a resist 25 for channel cutting is formed on the nitride film 23 and the insulating film 44, and window openings 26 are formed by ordinary photolithography. Ion implantation 27 is carried out.

In this case, the dose amount is 5×10 ¹² cm ⁻² and by implanting at 80 KeV, a channel cut region n ⁺ is formed in the n well 43 . Thereafter, the manufacturing steps from d to j in FIG. 9 are the same as the manufacturing steps from c to i in FIG. 10, low concentration diffusion regions 9 and 21 are formed, and the rest is the same, so repeated explanation will be omitted.

Note that FIGS. 9g to 9i show enlarged views of the well 43 portion.

Furthermore, if the concentrations of the low concentration diffusion regions 9 and 21 of the high voltage resistor 17a' are equal, the step shown in FIG. 9h can be omitted. Alternatively, ions may be implanted into the low concentration diffusion regions 9 and 21 at different doses using a mask as shown in FIG.

Further, when the channel stopper 11 is configured to be in contact with the low concentration diffusion region 21 as shown in FIG. 5, the channel stopper may be formed by the same manufacturing process as that shown in FIG. 8.

It is clear that these cases are completely the same as when forming a p channel in an n-type substrate, except that it is formed in the n-well 43.

The above explanation has been limited to the manufacturing process of the high voltage element 15 (15a) and the high voltage element 17'(17a'), but in reality, the integrated circuit 12
has a C-MOS configuration, and the reverse channel side is masked during the above manufacturing process. In addition, when manufacturing the reverse channel side, the high withstand voltage element 15 (15
a) and the high voltage resistor 17'(17a') can be considered to be masked.

(7) Effects of the Invention As described above in detail, according to the high voltage resistance element of the present invention, the depletion layer from the high impurity concentration regions 8 and 10 normally extends only to the substrate side, but in the present invention. In this case, since the low concentration region 21 surrounds the high impurity concentration regions 8 and 10 and spreads over a wide area as shown in FIGS. 4 and 5, the depletion layer is on the low concentration region 21 side. The pressure resistance can be further increased because the pressure is also expanded. In the case of Figure 4, the withstand voltage is -
In the case of Fig. 5, the withstand voltage could be increased to -30V or more.

The values at this time are the width of the low concentration region 9 between the two high concentration regions 8 and 10 of 10μ, the length of 100μ, the width of the low concentration region 21 of 3μ, and the distance between the low concentration region 21 and the channel stopper 11. This is the value selected for distance 22 at 3μ.

In addition, since high resistance values can be formed in fine patterns by arbitrarily selecting the dose of the low impurity concentration region, this greatly contributes to the miniaturization of high voltage integrated circuits.

Although the above embodiment describes an example in which it is applied to a high voltage device such as a fluorescent display tube, the high voltage resistance element of the present invention can be applied to a high voltage circuit that requires a high voltage resistance without being limited thereto. That is clear.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of a conventional MOS resistor, Figure 2 is a cross-sectional view of a conventional resistor in which a diffusion layer of high and low impurity concentration is formed on a substrate, and Figure 3 is a cross-sectional view of a conventional high voltage integrated circuit (fluorescent display). Figure 4 is a circuit diagram to explain the case where a high voltage resistor is used in a tube high voltage device).
5(a) and b are a side sectional view and a plan view of a high voltage resistance element of the present invention, and FIGS. Figures 6a to 6i are side sectional views showing the process of simultaneously forming a high voltage resistance element of the present invention as a high voltage resistance element (MOS transistor), and Figure 7 is a low impurity concentration region of the high voltage resistance element of the present invention. FIGS. 8a and 8b are side sectional views for explaining the formation method, and FIGS. FIG. 6 is a side sectional view showing a step of simultaneously forming a high voltage resistance element and a high voltage resistance element according to another embodiment of the present invention. 1...Substrate, 2...Thick insulating film, 3, 33, 4
4...Oxide film, 4,8,10...High impurity concentration diffusion region, 5a, 5b...Electrode window, 6...Insulating layer such as PSG, 7a, 7b, 7c...Al electrode, 9,
21, 39...Low impurity concentration diffusion region, 11...
Channel stopper, 12...Integrated circuit, 15,
15a... High voltage resistance element, 17... High voltage resistance resistor,
20... Fluorescent display tube, 23... Nitride film, 24,2
5, 28...Resist, 30...Gate oxide film,
36... Source region, 37... Drain region, 3
2... Gate electrode, 43... N-type well region, 1
6, 45... Pad, 17', 17a... High voltage resistance element.

Claims (1)

[Claims] 1. In an active region separated by a thick insulating film of a semiconductor substrate, two high impurity concentration regions of opposite conductivity type and spaced apart from the semiconductor substrate are formed at positions spaced apart from the thick insulating film. At the same time, a low impurity concentration region of the same conductivity type as the high impurity concentration region is formed between the two high impurity concentration regions and surrounding the entire periphery of the high impurity concentration region and in contact with the two high impurity concentration regions. . A semiconductor device comprising a high breakdown voltage resistance element formed by forming a channel stopper region of the same conductivity type as the semiconductor substrate under the thick insulating film. 2. The semiconductor device according to claim 1, wherein the channel stopper region is formed apart from the low impurity concentration region. 3. The semiconductor device according to claim 1, wherein the channel stopper region is formed in contact with the low impurity concentration region. 4. Claim 1, characterized in that the low impurity concentration region formed around the high impurity concentration region and the low impurity concentration region formed between the two high impurity concentration regions have different concentrations. 1. Semiconductor device described in Section 1.