JPH0454984B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a semiconductor device, and particularly to a high-speed, small-area bipolar transistor.

[Prior art]

Traditionally, bipolar ICs (Integrated Circuits)
A manufacturing method based on npn transistors is used. Due to restrictions on the manufacturing method, it is difficult to obtain high-performance PNP transistors. but,
In linear circuits, PNP transistors are also useful, and the performance of the entire circuit may be limited by the performance of the PNP transistor. Furthermore, in digital circuits, such as the integrated injection logic circuit I ² L, which uses a pnp transistor, higher performance of the pnp transistor is desired. As a way to improve the performance of pnp transistors, DSA as shown in Figure 1 is
(diffusion self align) is known. 1 is an n-type semiconductor layer, 2 is a p-type region that becomes a collector, 3 is an n-type region that becomes a base, 4 is a p-type region that becomes an emitter, 5 is an n-type region for taking out the base terminal, 7, 8, 9 are collector, emitter, and base electrodes, respectively, and 101 is an oxide film. In this method, since the base 3 and the emitter 4 are formed from the same diffusion window 6, the base width can be reduced with good controllability. However, since the base electrode is taken out via the n-type layer 1, the bottom surface of the emitter 4 does not face the collector. Therefore, the bottom surface of the emitter 4 becomes a parasitic pn junction, and when activated, holes are accumulated under the emitter 4, resulting in a significant drop in frequency characteristics.

In order to avoid the above drawbacks, a method as shown in FIG. 2 is taken. The symbols in the figure have the same meanings as those in FIG. 1. In this case, the base electrode is taken via the n-type region 5 provided on the front side. Therefore, the bottom part of the emitter 4 can also be made to face the collector 2, and the accumulated charge will be smaller than in the example shown in FIG. However, the distance between the emitter and the electrode extraction window of the base is large, and the area of the device is large. Assuming that there is a margin for alignment between the electrode extraction window and the metal electrode, and that the space between the metal electrodes is L ₂ , in the case of Figure 2, the distance between the emitter and the base electrode extraction window is 2L ₁ .
+L ₂ , and if L ₁ = 2μm and L ₂ = 3μm, then 7μ
A spacing of m is required. As mentioned above, the large interval means that the area of the region 5 becomes large, and the junction capacitance between the base and the collector becomes large, resulting in poor frequency characteristics. In addition, in Figures 1 and 2,
Details on the board side have been omitted.

[Purpose of the invention]

The purpose of the present invention is to eliminate the drawbacks of conventional structures and
The object of the present invention is to provide a transistor with a small area and good frequency characteristics.

[Summary of the invention]

The present invention reduces the distance between the emitter and the base electrode extraction window by extracting the base terminal of the transistor in the vertical direction using polycrystalline silicon.

A first method for manufacturing a semiconductor device of the present invention includes a first method for manufacturing a semiconductor device.
A step of forming a first opening in the nitride film 61 on the surface of the semiconductor substrate including the first semiconductor region 2 of the conductivity type, and a step of forming the polycrystalline semiconductor layer 90 containing a high concentration of impurities of the second conductivity type. forming an oxide film 55 on the surface of the polycrystalline semiconductor layer 90 by oxidizing the polycrystalline semiconductor layer 90; forming a second opening in the nitride film 61 by etching the nitride film 61 not covered by the oxide film 55 and the polycrystalline semiconductor layer 90 using the crystalline semiconductor layer 90 as a mask; By introducing the second conductivity type impurity and the first conductivity type impurity through the second opening, the second conductivity type impurity is introduced.
forming a second semiconductor region 3 of a conductivity type and a third semiconductor region 4 of a first conductivity type in the first semiconductor region 2 of the first conductivity type; The fourth semiconductor region 5 of the second conductivity type, which is formed by the diffusion of the impurity of the second conductivity type into the first semiconductor region, is in contact with the second semiconductor region 3.

According to the first method of manufacturing a semiconductor device of the present invention, the polycrystalline semiconductor layer 90 containing impurities of the second conductivity type at a high concentration and the third semiconductor region 4 of the first conductivity type
Since they are separated from each other by the nitride film 61, the reverse breakdown voltage between the polycrystalline semiconductor layer 90 and the third semiconductor region 4 can be increased (see FIG. 4).

Further, in the second method of manufacturing a semiconductor device of the present invention, a polycrystalline semiconductor layer 90 containing impurities of a second conductivity type at a high concentration is formed on the surface of the first semiconductor region 2 of the first conductivity type formed in the semiconductor substrate. a step of forming;
A second layer is formed into the first semiconductor region from the surface of the semiconductor substrate not covered by the polycrystalline semiconductor layer 90.
a step of forming a second semiconductor region 3 of a second conductivity type by introducing impurities of a conductivity type; After the step of forming an insulating film 55 on the substrate and the step of forming the second semiconductor region 3, the insulating film 55 is etched to form the opening located on the substrate surface of the second semiconductor region 3. The third semiconductor region 4 of the first conductivity type is formed by forming the film into a film and introducing impurities of the first conductivity type through the opening.
forming in the second semiconductor region 3 of the second conductivity type, by diffusing the impurity of the second conductivity type from the polycrystalline semiconductor layer 90 into the first semiconductor region 2. The fourth semiconductor region 5 of the second conductivity type to be formed is characterized in that it is in contact with the second semiconductor region 3.

According to the second method for manufacturing a semiconductor device of the present invention, the polycrystalline semiconductor layer 90 containing impurities of the second conductivity type at a high concentration and the third semiconductor region 4 of the first conductivity type
The polycrystalline semiconductor layer 9 is separated from the polycrystalline semiconductor layer 9 by an insulating film 55 patterned by etching after the step of forming the second semiconductor region 3 of the second conductivity type.
By performing etching to obtain a sufficient film thickness between the polycrystalline semiconductor layer 90 and the third semiconductor region 4, it is possible to increase the reverse breakdown voltage between the polycrystalline semiconductor layer 90 and the third semiconductor region 4. This becomes possible (see Figure 5).

[Embodiments of the invention]

A first embodiment of the present invention will be described below with reference to FIG. FIG. 3a is a sectional view, and FIG. 3b is a plan view. In the same figure, 2 to 8 mean the same things as in FIG. Further, 50 is a p-type substrate, 51 is a p-type substrate, and 51 is a p-type substrate.
n ⁺ buried layer, 52 is a lightly doped n-type or non-doped epitaxial layer, 53 is a p-type region, 54 is a thick oxide film, 55 is an oxide film, 10 is a p-type region for taking out the collector electrode, 90 is a This is an n-type polycrystalline silicon layer. In this embodiment, the emitter region 4
and base region 3 are formed from the same diffusion window 6. Window 6 is defined by oxide film 55 covering polycrystalline silicon 90. That is, the distance L between the emitter and the electrode extraction window of the base is determined only by the alignment when patterning the polycrystalline silicon 90 to match the electrode extraction window of the base. Note that the n-type regions 51 and 52 are used so as to be given a high potential so as to have a reverse bias with respect to the collector region 2.

This embodiment provides the following effects. The first effect is that since the emitter and base are formed by the same diffusion window, the base width can be narrowed with good controllability and a high current gain can be obtained. The second effect is that since the emitter faces the collector over almost the entire surface, the emitter junction works effectively and the current density is lowered compared to the case in Figure 1, so the current gain does not decrease even in the high current region. . The third effect is that the distance between the emitter and the electrode extraction window of the base can be set to about 1 to 2 μm because it is determined by one mask alignment for the above-mentioned reason. Therefore, compared to the case in Figure 2, it is 1/3 to 1/4
It can be doubled. Therefore, not only the area of the transistor itself can be reduced, but also the base-collector junction capacitance can be reduced, so that the frequency characteristics can be greatly improved.

FIG. 2b shows the plane pattern of FIG. 2a. A cross-sectional view along line A-A' looks like a. As shown in the figure, a base electrode extraction region 5 surrounds the emitter 4, and a collector electrode extraction region 10 surrounds the base electrode extraction region 5.

FIG. 4 shows the steps for obtaining the structure of the first embodiment.
This shows the manufacturing process. First, an n ⁺ region 51 is formed at a desired location on a p-type substrate 50, and an n-type or non-doped epitaxial layer 52 is formed, resulting in a structure as shown in FIG. Then, from the surface of 52, p
After forming the type region 2, forming the p-type region 53 for isolation, and further forming a thick oxide film 54 by selective oxidation, the result is as shown in FIG. Next, as shown in figure c,
A thin oxide film 60 is formed on the surface, and a nitride film 61 is further formed on the surface.
are formed, and holes 60 and 61 are selectively opened. Next, a polycrystalline silicon layer 90 containing a high concentration of n-type impurity is provided so as to cover the windows 60 and 61, and oxidized to form an oxide film 55 on the surface of the layer 90. At this time, since the surface of region 2 is covered with the nitride film 61, no oxide film grows on the surface of region 2, resulting in a state as shown in FIG. d. Next, the nitride film is etched to form a base region 3 and an emitter region 4 as shown in FIG. To form the base region 3, the extraction window of the collector electrode is covered with photoresist and ion implantation is performed. Moreover, the extraction region 10 of the collector electrode can be formed simultaneously with 4. A structure like e can be obtained by applying appropriate heat treatment. Note that the base electrode extraction region 5 is obtained by adding impurities from 90. Further, it is preferable to use phosphorus to form the base 3. Since phosphorus has a large diffusion coefficient, it can be brought into contact with 5 relatively easily. Next, by providing metal electrodes for the emitter and collector, the structure shown in FIG. 3 is obtained.

FIG. 5 shows the steps for obtaining the structure of the second embodiment.
This shows the manufacturing process. The steps up to a in FIG. 4 are the same as the steps up to FIG. 4b. Next, in this step, as shown in FIG. 5B, a polycrystalline silicon layer 90 containing a high concentration of n-type impurities is provided at a desired location in region 2. Next, as shown in FIG. 3C, a base layer 3 is provided by ion implantation of n-type impurities. Ion implantation can be selectively performed using photoresist. When heat treatment is performed after ion implantation, region 5 can be formed by diffusion of impurities from 90 as shown in FIG. Next, as shown in FIG. 4D, the surface is covered with an oxide film 55, windows for taking out the emitter and collector electrodes are opened, and p-type impurity ions are implanted to obtain 4 and 10. Furthermore, by forming metal electrodes for the emitter and coecter, the structure shown in the figure e is obtained. In this embodiment, although the emitter and base are not formed from the same diffusion window, it has the advantage that contact between regions 3 and 5 is facilitated. The effects of this structure are similar to those of the first embodiment.

FIG. 6 shows a third embodiment of the invention. In this embodiment, a heavily doped p-type impurity region 56 is provided at the bottom of region 2. In this way, the collector series resistance from just below the emitter to the collector electrode can be reduced. 56 can be formed by burying a p-type impurity so as to overlap with the n-type buried layer 51. When antimony is used for 51 and boron is used for 56, boron rises up more and can be formed so as to come into contact with region 2.

FIG. 7 shows a fourth embodiment of the invention. In this example, the present invention is used in the injector portion of I ² L. 51 is an n-type region, which is a buried layer or an n-type substrate. 2, 3, 4, 5, 8, 5
4, 55, and 90 represent the same items as in FIG.
Furthermore, 11 is an n-type region, 12 is a p-type region, and 13 is a metal electrode. 4, 3, 2 are the emitter, base, and collector of the pnp transistor, and 51,
2 and 11 are the emitter, base, and collector of the npn transistor. 5 and 11, 4 and 12 can be formed at the same time. The following effects can be obtained from this embodiment. The first effect is that, as described in the first embodiment, the current gain of the injector can be increased, so that the power consumption-delay time product of I ² L can be reduced. The second effect depends on being able to control the potential at the base of the injector. Therefore, the junctions of regions 2 and 3 in FIG. 7 are operated in order so as not to become biased, so that the charge accumulated in region 3 is reduced and the speed of I ² L can be improved. In particular, when the dimensions of the element are miniaturized, the I ² L characteristics are greatly affected by the characteristics of the injector, so as in this example, the distance between the base electrode of the injector and the emitter electrode of the injector can be reduced to 2 μm or less. The structure is very effective.

〔Effect of the invention〕

According to the present invention, the distance between the emitter electrode and the base electrode of a transistor operating in the vertical direction can be reduced to 2 μm or less. This is 1/3 to 1/4 of the conventional method,
The effect is huge. Furthermore, the overall dimensions of the device are significantly reduced, resulting in reduced junction capacitance and improved frequency characteristics.

[Brief explanation of the drawing]

Figures 1 and 2 are sectional views of the conventional structure, Figure 3 is a sectional view and plan view of the first embodiment, and Figure 4 explains the manufacturing process for obtaining the structure of the first embodiment. 5 is a sectional view of the device explaining the manufacturing process for obtaining the structure of the second embodiment, FIG. 6 is a sectional view of the third embodiment, and FIG. 7 is the fourth embodiment. FIG. 1...n type region, 2...p type region, 3...n type base region, 4...p type emitter region, 5...n
Mold base electrode extraction area, 6...Diffusion window of emitter and base, 7...Collector electrode, 8...Emitter electrode, 9...Base electrode, 10...Collector electrode extraction area, 11...I ² L collector region,
12...I ² L base electrode extraction area, 13...
...I ² L base electrode, 50...p-type substrate, 51...
...N-type buried layer, 52...Epitaxial layer, 53
... p-type region, 54 ... thick oxide film, 55 ... oxide film, 56 ... p-type buried layer, 60 ... thin oxide film, 61 ... nitride film, 90 ... polycrystalline silicon,
101...Oxide film.

Claims (1)

[Claims] 1. A step of forming a first opening in a nitride film on a surface of a semiconductor substrate including a first semiconductor region of a first conductivity type, and a polycrystalline film containing a high concentration of impurities of a second conductivity type. forming a semiconductor layer to at least cover the first opening; forming an oxide film on the surface of the polycrystalline semiconductor layer by oxidizing the polycrystalline semiconductor layer; forming a second opening in the nitride film by etching the oxide film and the nitride film not covered by the polycrystalline semiconductor layer using the polycrystalline semiconductor layer as a mask; By introducing an impurity of the second conductivity type and an impurity of the first conductivity type through the opening, a second semiconductor region of the second conductivity type and a third semiconductor region of the first conductivity type are formed.
forming a semiconductor region in the first semiconductor region of the first conductivity type, and during the step of forming the second semiconductor region of the second conductivity type, forming a semiconductor region from the polycrystalline semiconductor layer in the first semiconductor region of the first conductivity type. A fourth semiconductor region of a second conductivity type formed by diffusion of the impurity of the second conductivity type into one semiconductor region is in contact with the second semiconductor region; A method of manufacturing a semiconductor device, wherein the second semiconductor region, the third semiconductor region, and the fourth semiconductor region are a collector region, a base region, an emitter region, and a base electrode lead-out region of a transistor, respectively. 2. The method of manufacturing a semiconductor device according to claim 1, wherein the transistor is a charge injection element of an integrated injection logic circuit. 3. Forming a polycrystalline semiconductor layer containing a high concentration of impurities of a second conductivity type on the surface of a first semiconductor region of a first conductivity type formed on a semiconductor substrate, and covering with the polycrystalline semiconductor layer. forming a second semiconductor region of a second conductivity type by introducing an impurity of a second conductivity type into the first semiconductor region from a surface of the semiconductor substrate that is not covered with the polycrystalline semiconductor layer; forming an insulating film on the surface of the semiconductor substrate and on the polycrystalline semiconductor layer, and etching the insulating film after the step of forming the second semiconductor region. forming an opening in the insulating film located on the surface of the substrate; and introducing a first conductivity type impurity through the opening to form a third conductivity type impurity.
forming a semiconductor region in the second semiconductor region of the second conductivity type, wherein during the step of forming the second semiconductor region of the second conductivity type, the polycrystalline semiconductor layer is A fourth semiconductor region of a second conductivity type formed by diffusion of the impurity of the second conductivity type into the semiconductor region is in contact with the second semiconductor region; 2. A method of manufacturing a semiconductor device, wherein the second semiconductor region, the third semiconductor region, and the fourth semiconductor region are a collector region, a base region, an emitter region, and a base electrode lead-out region of a transistor, respectively. 4. The method of manufacturing a semiconductor device according to claim 3, wherein the transistor is a charge injection element of an integrated injection logic circuit.