JPH0455333B2 - - Google Patents

Info

Publication number
JPH0455333B2
JPH0455333B2 JP60189759A JP18975985A JPH0455333B2 JP H0455333 B2 JPH0455333 B2 JP H0455333B2 JP 60189759 A JP60189759 A JP 60189759A JP 18975985 A JP18975985 A JP 18975985A JP H0455333 B2 JPH0455333 B2 JP H0455333B2
Authority
JP
Japan
Prior art keywords
pad
bonding
transistor
pads
switching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60189759A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6251231A (ja
Inventor
Kimiaki Sato
Yoshihiro Takemae
Shigeki Nozaki
Masao Nakano
Osami Kodama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60189759A priority Critical patent/JPS6251231A/ja
Publication of JPS6251231A publication Critical patent/JPS6251231A/ja
Publication of JPH0455333B2 publication Critical patent/JPH0455333B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)
JP60189759A 1985-08-30 1985-08-30 半導体集積回路装置 Granted JPS6251231A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60189759A JPS6251231A (ja) 1985-08-30 1985-08-30 半導体集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60189759A JPS6251231A (ja) 1985-08-30 1985-08-30 半導体集積回路装置

Publications (2)

Publication Number Publication Date
JPS6251231A JPS6251231A (ja) 1987-03-05
JPH0455333B2 true JPH0455333B2 (cs) 1992-09-03

Family

ID=16246700

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60189759A Granted JPS6251231A (ja) 1985-08-30 1985-08-30 半導体集積回路装置

Country Status (1)

Country Link
JP (1) JPS6251231A (cs)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2605687B2 (ja) * 1986-04-17 1997-04-30 三菱電機株式会社 半導体装置
KR100465872B1 (ko) * 1997-09-04 2005-05-17 삼성전자주식회사 오픈드레인및풀업회로
JP4246237B2 (ja) 2007-02-05 2009-04-02 株式会社オーバル ポンプユニット式サーボ型容積流量計

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0763066B2 (ja) * 1983-06-29 1995-07-05 富士通株式会社 半導体装置

Also Published As

Publication number Publication date
JPS6251231A (ja) 1987-03-05

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