JPH0455556B2 - - Google Patents
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- Publication number
- JPH0455556B2 JPH0455556B2 JP61303527A JP30352786A JPH0455556B2 JP H0455556 B2 JPH0455556 B2 JP H0455556B2 JP 61303527 A JP61303527 A JP 61303527A JP 30352786 A JP30352786 A JP 30352786A JP H0455556 B2 JPH0455556 B2 JP H0455556B2
- Authority
- JP
- Japan
- Prior art keywords
- layer
- insulating layer
- circuit board
- opening
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は多層配線回路基板に関する。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a multilayer wiring circuit board.
（従来の技術）
従来から絶縁基板上に、導体パターン層と絶縁
層とが所定の層数だけ積層された多層配線回路基
板を製造する方法として、例えば次のような方法
が知られている。すなわち第２図ａおよび第２図
ｂに示すように、まずセラミツクス基板等の絶縁
基板１上に、マスクによる選択蒸着あるいは全面
蒸着後の通常のフオトリソ工程により第１の導体
パターン層２ａが形成する。次にこの導体パター
ン層２ａ上に第１の絶縁層３ａを全面に被着形成
したのち、エツチングマスクを大きくするか、あ
るいはオーバーエツチングにより所望の導体間接
続部の断面積よりも大きい導体間接続用の開口部
４ａを形成する。続いて同様の方法により第２の
絶縁層３ｂを全面に被着形成し、所望の導体間接
続部（貫通孔）の断面積と等しい大きさの導体間
接続用の開口部４ｂを形成する。こののち第２の
導体パターン層２ｂをマスクによる選択蒸着ある
いは全面蒸着後の通常のフオトリソ工程により所
望のパターンに形成する。(Prior Art) As a method for manufacturing a multilayer wiring circuit board in which a predetermined number of conductor pattern layers and insulating layers are laminated on an insulating substrate, for example, the following method is known. That is, as shown in FIGS. 2a and 2b, first, a first conductor pattern layer 2a is formed on an insulating substrate 1 such as a ceramic substrate by selective vapor deposition using a mask or by a normal photolithography process after full-surface vapor deposition. . Next, after forming a first insulating layer 3a on the entire surface of the conductor pattern layer 2a, the etching mask is enlarged or over-etching is performed to form a conductor-to-conductor connection larger than the desired cross-sectional area of the conductor-to-conductor connection. An opening 4a is formed for the purpose. Subsequently, a second insulating layer 3b is deposited on the entire surface by a similar method, and an opening 4b for connecting between conductors is formed with a size equal to the cross-sectional area of the desired inter-conductor connecting portion (through hole). Thereafter, the second conductive pattern layer 2b is formed into a desired pattern by selective vapor deposition using a mask or by a normal photolithography process after full surface vapor deposition.
（発明が解決しようとする問題点）
しかしながらこのようにして得られた従来の多
層配線回路基板では、第１の絶縁層３ａおよび第
２の絶縁層３ｂの開口部を形成する際に、第２図
ｃに示すように開口部４ａ，４ｂの角部等で絶縁
層の膜残り５ａ，５ｂが生じる。この膜残りは絶
縁層の材料として感光性ポリイミドを使用した場
合に特に顕著である。このように実質的な貫通孔
となる第２の絶縁層の開口部４ｂに膜残り５ｂが
生じると第１の導体パターン層２ａと第２の導体
パターン層２ｂとの接続面積が減少し、接続不良
が生ずるという問題があつた。(Problems to be Solved by the Invention) However, in the conventional multilayer wiring circuit board obtained in this way, when forming the openings in the first insulating layer 3a and the second insulating layer 3b, the second As shown in FIG. c, film residues 5a and 5b of the insulating layer are formed at the corners of the openings 4a and 4b. This film residue is particularly noticeable when photosensitive polyimide is used as the material for the insulating layer. If the remaining film 5b is formed in the opening 4b of the second insulating layer, which essentially becomes a through hole, the connection area between the first conductor pattern layer 2a and the second conductor pattern layer 2b decreases, and the connection There was a problem that defects occurred.
本発明はこのような問題を解決するためになさ
れたもので、絶縁層開口部の膜残りによる接続不
良を少なくして歩留りを向上させた多層配線回路
基板を提供することを目的とする。 The present invention has been made to solve these problems, and an object of the present invention is to provide a multilayer wiring circuit board that improves yield by reducing connection failures due to film residue in the openings of the insulating layer.
［発明の構成］
（問題点を解決するための手段）
本発明の多層配線回路基板は、絶縁基板上に導
体パターン層が２層構造の絶縁層を介して所定の
層数だけ積層され、前記２層構造の絶縁層に上下
に隣接する導体パターン層を接続するための貫通
孔が形成された多層配線回路基板において、前記
貫通孔を構成する２層の絶縁層のそれぞれの開口
部を、平行な長辺を有する細長形状に形成し、か
つ互いに長手方向がほぼ直角に交差するように形
成したことを特徴としている。[Structure of the Invention] (Means for Solving the Problems) The multilayer wiring circuit board of the present invention includes a predetermined number of conductor pattern layers laminated on an insulating substrate via an insulating layer having a two-layer structure, and In a multilayer wiring circuit board in which a through hole is formed in an insulating layer having a two-layer structure to connect vertically adjacent conductor pattern layers, the openings of the two insulating layers constituting the through hole are arranged in parallel. It is characterized in that it is formed into an elongated shape with long sides, and its longitudinal directions intersect with each other at approximately right angles.
絶縁層の開口部の形状としては長方形が適して
いるが、俵型その他任意の互いに平行な２つの長
辺を有する形状とすることができる。また本発明
においては２層の絶縁層のうち外側の層は内側の
層より薄くすることが望ましい。 Although a rectangular shape is suitable for the shape of the opening in the insulating layer, it can also be formed into a barrel shape or any other shape having two long sides parallel to each other. Further, in the present invention, it is desirable that the outer layer of the two insulating layers be thinner than the inner layer.
（作用）
このように各絶縁層の開口部を互いに平行な２
つの長辺を有する細長形状にしてそれらがほぼ直
交するように形成することにより、それぞれの開
口部に膜残りが発生しても必要な大きさの導体間
接続用貫通孔は確保されるため、膜残りによる接
続不良がほとんど生じなくなる。(Function) In this way, the openings of each insulating layer are
By forming an elongated shape with two long sides so that they are almost orthogonal, even if film remains at each opening, a through hole of the necessary size for connecting conductors can be secured. Connection failures due to film residue almost no longer occur.
さらに、本発明においては、第１の導体パター
ン層と第２の導体パターン層との接続部分のうち
下層の導体パターンと平行する辺の周囲は２層の
絶縁層のうち外側の層のみが介在することになる
ので、この外側の層を内側の層より薄くすること
により、第２の導体パターン層の段切れによる接
続不良を防止することができる。 Furthermore, in the present invention, only the outer layer of the two insulating layers is interposed around the side parallel to the lower layer conductor pattern in the connecting portion between the first conductor pattern layer and the second conductor pattern layer. Therefore, by making this outer layer thinner than the inner layer, it is possible to prevent connection failures due to step breaks in the second conductive pattern layer.
（実施例）
次に本発明の実施例について図面を用いて説明
する。(Example) Next, an example of the present invention will be described using the drawings.
第１図ａは本発明の多層配線回路基板の平面
図、第１図ｂは第１図ａのＡ−A′線に沿つて切
断した断面図、第１図ｃは開口部の拡大図であ
る。図において符号１１はセラミツクス基板等の
絶縁基板、符号１２ａは絶縁基板１１上に形成さ
れた第１の導体パターン層で、さらにその上に感
光性ポリイミドからなる第１の絶縁層１３ａと第
２の絶縁層１３ｂおよび第２の導体パターン層１
２ｂが形成されている。各絶縁層には第１の導体
パターン層１２ａと第２の導体パターン層１２ｂ
とを接続するための導体間接続用の開口部１４
ａ，１４ｂが形成されている。これらの開口部は
第１図ｃに示すように、第１の絶縁層１３ａの開
口部１４ａは長辺が第１の導体パターン層１２ａ
の配線方向と直交する長方形になるよう形成され
ており、第２の絶縁層１３ｂの開口部１４ｂは長
辺が第１の絶縁層１３ａの開口部１４ａの長辺と
直交する長方形になるように形成されている。 Figure 1a is a plan view of the multilayer wiring circuit board of the present invention, Figure 1b is a sectional view taken along line A-A' in Figure 1a, and Figure 1c is an enlarged view of the opening. be. In the figure, reference numeral 11 is an insulating substrate such as a ceramic substrate, reference numeral 12a is a first conductor pattern layer formed on the insulating substrate 11, and a first insulating layer 13a made of photosensitive polyimide and a second conductor pattern layer are further formed on the insulating substrate 11. Insulating layer 13b and second conductor pattern layer 1
2b is formed. Each insulating layer has a first conductor pattern layer 12a and a second conductor pattern layer 12b.
Opening 14 for connecting between conductors
a, 14b are formed. As shown in FIG. 1c, the openings 14a of the first insulating layer 13a have long sides facing the first conductor pattern layer 12a.
The opening 14b of the second insulating layer 13b is formed into a rectangle whose long side is perpendicular to the long side of the opening 14a of the first insulating layer 13a. It is formed.
本発明の多層配線回路基板は例えば次のように
して製造される。 The multilayer wiring circuit board of the present invention is manufactured, for example, as follows.
まず絶縁基板１１の全面にTiを真空蒸着し、
通常のフオトリソ工程により所望のパターンを有
する第１の導体パターン層１２ａを形成する。次
にその全面に感光性ポリイミドを厚く被着形成
し、フオトマクスを使用して露光現象工程により
所定の位置に開口部１４ａを設けて第１の絶縁層
１３ａを形成する。この際フオトマスクとして開
口部が長方形で、その長辺が第１の導体パターン
層１２ａの配線方向と直交するように、かつその
幅が第２の導体パターン層１２ｂの配線幅よりも
短いパターンの形成されたものを使用する。続い
て感光性ポリイミドを第１の絶縁層１３ａより薄
く全面に被着形成し、フオトマスクを使用して同
様に開口部１４ｂを設けて第２の絶縁層１３ｂを
形成する。この際フオトマスクとして開口部が長
方形で、その長辺が第１の絶縁層１３ａの開口部
１４ａの長辺と直交するように、かつその幅が第
１の導体パターン層１２ａの配線幅よりも短いパ
ターンの形成されたものを使用する。 First, Ti is vacuum-deposited on the entire surface of the insulating substrate 11,
A first conductor pattern layer 12a having a desired pattern is formed by a normal photolithography process. Next, a thick layer of photosensitive polyimide is deposited on the entire surface, and an opening 14a is formed at a predetermined position by an exposure process using a photomask to form a first insulating layer 13a. At this time, a pattern is formed as a photomask such that the opening is rectangular, its long side is perpendicular to the wiring direction of the first conductive pattern layer 12a, and its width is shorter than the wiring width of the second conductive pattern layer 12b. Use what was given. Subsequently, photosensitive polyimide is deposited on the entire surface to be thinner than the first insulating layer 13a, and openings 14b are similarly provided using a photomask to form the second insulating layer 13b. At this time, the photomask has a rectangular opening, and its long side is perpendicular to the long side of the opening 14a of the first insulating layer 13a, and its width is shorter than the wiring width of the first conductive pattern layer 12a. Use one with a pattern formed on it.
しかる後、第２の絶縁層１３ｂの全面にTiを
真空蒸着し、通常のフオトリソ工程により所望の
パターンで第２の導体パターン層１２ｂを形成す
る。 Thereafter, Ti is vacuum-deposited on the entire surface of the second insulating layer 13b, and a second conductive pattern layer 12b is formed in a desired pattern by a normal photolithography process.
このようにして製造した多層配線回路基板で
は、各長方形状の開口部１４ａ，１４ｂがそれぞ
れ長辺を直交させて配置されているので、第１図
ｃに示すように、膜残り１５ａ，１５ｂが発生し
てもこの部分は２つの絶縁層１３ａ，１３ｂを貫
通する実質的な貫通孔から外れた位置となり、し
たがつて必要な大きさの導体接続部が得られるの
で膜残りによる接続不良が解消される。またこの
実施例では第１の導体パターン層１２ａと第２の
導体パターン層１２ｂとが交差する領域で第１の
導体パターン層１２ａと平行な開口部１４ｂの長
辺の周囲が薄い第２の絶縁層１３ｂを介している
ので、第２の導体パターン層１２ｂの段切れが防
止され、段切れによる接続不良が解消される。 In the multilayer wiring circuit board manufactured in this way, the rectangular openings 14a and 14b are arranged with their long sides perpendicular to each other, so that the remaining films 15a and 15b are removed as shown in FIG. 1c. Even if this occurs, this portion will be located outside the actual through hole that penetrates the two insulating layers 13a and 13b, and therefore a conductor connection portion of the necessary size can be obtained, eliminating connection failures due to film residue. be done. Further, in this embodiment, in the area where the first conductive pattern layer 12a and the second conductive pattern layer 12b intersect, the periphery of the long side of the opening 14b parallel to the first conductive pattern layer 12a is thin. Since the second conductor pattern layer 12b is interposed through the layer 13b, breakage of the second conductive pattern layer 12b is prevented, and poor connection due to breakage is eliminated.
なお上述の実施例では２層の導体パターン層を
有する多層配線回路基板の例について説明した
が、これより層数の多い多層配線基板にも同様に
適用可能である。また第１の導体パターン層、第
２の導体パターン層ともにTiを使用したが、Ti
以外の金属を使用してもよく、第１の導体パター
ン層と第２の導体パターン層とで異なる金属を使
用してもよい。さらに開口部の形状も長方形に限
らず俵型その他の平行する２つの長辺を有する他
の形状とすることも可能である。 In the above-mentioned embodiment, an example of a multilayer wiring circuit board having two conductive pattern layers has been described, but the present invention can be similarly applied to a multilayer wiring board having a larger number of layers. Furthermore, although Ti was used for both the first conductor pattern layer and the second conductor pattern layer, Ti
Alternatively, different metals may be used for the first conductor pattern layer and the second conductor pattern layer. Further, the shape of the opening is not limited to a rectangle, but may be a barrel shape or other shape having two parallel long sides.
以上説明したように、上記構成の多層配線回路
基板においては、導体パターン層間に介在し両導
体パターン層間を電気的に接続する導体が配設さ
れる２層構成の絶縁層の各開口部がそれぞれ直交
するように形成されるので、膜残りが発生しても
必要な大きさの開口部が得られ、膜残りによる接
続不良がなくなる。さらに、２層構成の絶縁層の
うち外側の層を内側より薄くすれば、第１の導体
パターン層と第２の導体パターン層との接続部分
において外側の絶縁層の開口部の長辺の周囲がよ
り薄くなるので段切れによる接続不良を防止する
ことができる。 As explained above, in the multilayer wiring circuit board having the above structure, each opening of the insulating layer of the two-layer structure in which the conductor intervening between the conductor pattern layers and electrically connecting both conductor pattern layers is disposed is provided. Since they are formed perpendicularly, an opening of the necessary size can be obtained even if film remains, and connection failures due to film remains are eliminated. Furthermore, if the outer layer of the two-layer insulating layer is made thinner than the inner layer, the periphery of the long side of the opening in the outer insulating layer at the connecting portion between the first conductive pattern layer and the second conductive pattern layer Since it becomes thinner, it is possible to prevent connection failures due to breakage.
［発明の効果］
以上の説明からも明らかなように、本発明によ
れば、上下に隣接する導体パターン層を接続する
ために必要な大きさの貫通孔が得られ、膜残りに
よる接続不良がなくなり、歩留りが向上するとと
もに工程の管理が容易になる。[Effects of the Invention] As is clear from the above description, according to the present invention, a through hole of a size necessary to connect vertically adjacent conductor pattern layers can be obtained, and connection failures due to film residue can be avoided. This improves yield and makes process management easier.
第１図ａは本発明の多層配線回路基板の平面
図、第１図ｂは第１図ａのＡ−A′線に沿つて切
断した断面図、第１図ｃは本発明における開口部
の拡大図、第２図ａは従来の多層配線回路基板の
平面図、第２図ｂは第２図ａのＢ−B′線に沿つ
て切断した断面図、第２図ｃは従来の開口部の拡
大図である。
１，１１……絶縁基板、２ａ，１２ａ……第１
の導体パターン層、２ｂ，１２ｂ……第２の導体
パターン層、３ａ，１３ａ……第１の絶縁層、３
ｂ，１３ｂ……第２の絶縁層、４ａ，１４ａ……
第１の絶縁層に形成された開口部、４ｂ，１４ｂ
……第２の絶縁層に形成された開口部、５ａ，１
５ａ……第１の絶縁層における開口部の膜残り、
５ｂ，１５ｂ……第２の絶縁層における開口部の
膜残り。
FIG. 1a is a plan view of a multilayer wiring circuit board according to the present invention, FIG. 1b is a cross-sectional view taken along line A-A' in FIG. 1a, and FIG. An enlarged view, FIG. 2a is a plan view of a conventional multilayer wiring circuit board, FIG. 2b is a sectional view taken along line B-B' in FIG. 2a, and FIG. 2c is a conventional opening. It is an enlarged view of. 1, 11...Insulating substrate, 2a, 12a...First
conductor pattern layer, 2b, 12b... second conductor pattern layer, 3a, 13a... first insulating layer, 3
b, 13b... second insulating layer, 4a, 14a...
Openings formed in the first insulating layer, 4b, 14b
...opening formed in the second insulating layer, 5a, 1
5a... Remaining film at the opening in the first insulating layer,
5b, 15b...Remaining film at the opening in the second insulating layer.
Claims (1)
縁層を介して所定の層数だけ積層され、前記２層
構造の絶縁層に上下に隣接する導体パターン層を
接続するための貫通孔が形成された多層配線回路
基板において、前記貫通孔を構成する２層の絶縁
層のそれぞれの開口部を、平行な長辺を有する細
長形状に形成し、かつ互いに長手方向がほぼ直角
に交差するように形成したことを特徴とする多層
配線回路基板。 ２ 開口部の形状が長方形であることを特徴とす
る特許請求の範囲第１項記載の多層配線回路基
板。 ３ 絶縁層の開口部をその長手方向がこの絶縁層
に接する導体パターン層の配線方向とほぼ直交す
るように形成し、かつこの開口部の長辺の間隔を
この絶縁層に接しない側の導体パターン層の配線
幅よりも短く形成したことを特徴とする特許請求
の範囲第１項または第２項記載の多層配線回路基
板。 ４ ２層の絶縁層のうち外側の層が内側の層より
薄く形成されていることを特徴とする特許請求の
範囲第１項ないし第３項のいずれか１項記載の多
層配線回路基板。[Claims] 1. A predetermined number of conductive pattern layers are laminated on an insulating substrate via a two-layer insulating layer, and vertically adjacent conductive pattern layers are connected to the two-layer insulating layer. In a multilayer wiring circuit board in which a through hole is formed, each opening of the two insulating layers constituting the through hole is formed into an elongated shape with parallel long sides, and the longitudinal direction is substantially parallel to each other. A multilayer wiring circuit board characterized by being formed so as to intersect at right angles. 2. The multilayer wiring circuit board according to claim 1, wherein the opening has a rectangular shape. 3 The opening in the insulating layer is formed so that its longitudinal direction is substantially perpendicular to the wiring direction of the conductor pattern layer that is in contact with this insulating layer, and the distance between the long sides of this opening is set to be equal to the distance between the long sides of the conductor on the side that is not in contact with this insulating layer. 3. The multilayer wiring circuit board according to claim 1, wherein the multilayer wiring circuit board is formed to have a width shorter than the wiring width of the pattern layer. 4. The multilayer wiring circuit board according to any one of claims 1 to 3, wherein the outer layer of the two insulating layers is formed thinner than the inner layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30352786A JPS63155691A (en) | 1986-12-18 | 1986-12-18 | Maltilayer interconnection circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP30352786A JPS63155691A (en) | 1986-12-18 | 1986-12-18 | Maltilayer interconnection circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63155691A JPS63155691A (en) | 1988-06-28 |
| JPH0455556B2 true JPH0455556B2 (en) | 1992-09-03 |
Family
ID=17922060
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP30352786A Granted JPS63155691A (en) | 1986-12-18 | 1986-12-18 | Maltilayer interconnection circuit board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63155691A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1992009102A1 (en) * | 1990-11-15 | 1992-05-29 | International Business Machines Corporation | A method of making a multilayer thin film structure |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6196796A (en) * | 1984-10-17 | 1986-05-15 | 株式会社日立製作所 | multilayer wiring board |
-
1986
- 1986-12-18 JP JP30352786A patent/JPS63155691A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63155691A (en) | 1988-06-28 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |