JPH0455906A - Method and device for high speed interruption type control of sequencer - Google Patents

Method and device for high speed interruption type control of sequencer

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Publication number
JPH0455906A
JPH0455906A JP16703490A JP16703490A JPH0455906A JP H0455906 A JPH0455906 A JP H0455906A JP 16703490 A JP16703490 A JP 16703490A JP 16703490 A JP16703490 A JP 16703490A JP H0455906 A JPH0455906 A JP H0455906A
Authority
JP
Japan
Prior art keywords
processing
interruption
high speed
control
interrupt
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16703490A
Other languages
Japanese (ja)
Inventor
Yasuo Shimomura
霜村 恭雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP16703490A priority Critical patent/JPH0455906A/en
Publication of JPH0455906A publication Critical patent/JPH0455906A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To attain the effective execution of a ladder by dividing the ladder sequence control into two parts, i.e., the normal repetitive control and the high speed interruption control. CONSTITUTION:Some signals requiring the high speed response are fetched by an interruption condition deciding part 200 out of those signals inputted through a control signal input part 100. The part 200 decides whether the high speed interruption processing should be carried out or not based on the interruption grant signal received from an input/output signal control part 403. If the high speed interruption is granted, a processing start address is produced at an interruption address generating part 300 in response to an interruption signal. Then the corresponding interruption processing is started at a high speed interruption control part 401 included in a ladder sequence control part 400. Meanwhile the normal processing is carried out among the parts 100 and 403 and a repetitive control part 402 in a normal state where no high speed interruption processing is carried out at and after a power supply is turned on.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はシーケンサの高速割込み型制御方法および装置
、特にラダ一方式のシーケンサの高速割込み型制御方法
および装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a high-speed interrupt-type control method and apparatus for a sequencer, and particularly to a high-speed interrupt-type control method and apparatus for a ladder-type sequencer.

〔従来の技術〕[Conventional technology]

従来、この種のセンサは、ラダー図でプログラミングさ
れたラダーを先頭から遂次実行し、最後のラダーを実行
すると再び先頭のラダーに戻るというように繰り返し方
式により制御していた。
Conventionally, this type of sensor has been controlled by a repeating method, in which ladders programmed in a ladder diagram are executed one after another from the beginning, and when the last ladder is executed, the program returns to the first ladder.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の技術は、必ず先頭から最後までラダーを
逐一実行するのでラダーのステップサイズが大きくなる
と、1周期の実行時間が長くなり、制御対象の装置に要
求される応答時間を満足出来な(なると共に、特に高速
で応答したい制御対象に対しては処理出来ないという欠
点がある。
In the conventional technology described above, the ladder is always executed one by one from the beginning to the end, so when the step size of the ladder becomes large, the execution time for one cycle becomes longer and the response time required of the device to be controlled cannot be satisfied ( In addition, it has the disadvantage that it cannot process a controlled object that requires particularly high-speed response.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のシーケンサの高速割込み型制御装置は、制御対
象の作業を2つに分けており、1つは、繰り返し処理を
実行する繰り返し制御部と、又もう一方は、高速応答を
可能とするために制御対象信号を確認し、高速応答を行
うか否かの判定を行うと共に、割込み処理番地を発生さ
せその処理を実行する高速割込み制御部とを有している
The high-speed interrupt control device for a sequencer of the present invention divides the work to be controlled into two parts: one is a repetition control part that executes repetitive processing, and the other part is used to enable high-speed response. The high-speed interrupt control section checks the signal to be controlled and determines whether or not to perform a high-speed response, generates an interrupt processing address, and executes the processing.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing one embodiment of the present invention.

制御信号入出力部100より入力される信号のうち、高
速応答を必要とする信号の一部を割込み条件判定部20
0に取り込み、入出力信号制御部403からの割込み許
可信号により高速割込み処理を行うか否かが判定される
Among the signals inputted from the control signal input/output section 100, some of the signals that require high-speed response are sent to the interrupt condition determination section 20.
0, and it is determined whether or not to perform high-speed interrupt processing based on the interrupt permission signal from the input/output signal control unit 403.

割込み許可となった場合は、割込み信号に応じた処理開
始番地が割込み番地発生部300で発生し、ラダーシー
ケンス制御部400の中の高速割込み制御部401の相
当する割込み処理が開始される。
If the interrupt is permitted, a processing start address corresponding to the interrupt signal is generated in the interrupt address generation section 300, and the corresponding interrupt processing in the high speed interrupt control section 401 in the ladder sequence control section 400 is started.

一方、電源ON時以降、高速割込み処理が発生していな
い通常の場合は制御信号入出力部100、入出力制御部
403.繰り返し制御部402の間で通常処理が実行さ
れる。
On the other hand, in a normal case where no high-speed interrupt processing has occurred since the power was turned on, the control signal input/output unit 100, the input/output control unit 403. Normal processing is executed between the repetition control unit 402.

第2図では、繰り返し制御部の通常処理と高速割込み制
御部の割込み処理(1,2・・・n)が並行して実行さ
れることを示す。
FIG. 2 shows that the normal processing of the repetition control section and the interrupt processing (1, 2, . . . n) of the high-speed interrupt control section are executed in parallel.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ラダーシーケンス制御を
2つに分割し、1つは、通常の繰り返し制御を、又もう
1方は、高速割込み制御を行うことにより、高速応答を
必要とする処理を低速でもよい処理と分離すると共に、
高速応答処理の中でも割込み順位の初期設定の仕方によ
り、割込みのひん度や処理の優先度等への対応を考慮出
来、ラダーの効率的な実行を可能にすることが出来る効
果がある。
As explained above, the present invention divides ladder sequence control into two parts; one part performs normal repeat control and the other part performs high-speed interrupt control, thereby processing processes that require high-speed response. In addition to separating processing from processing that can be performed at low speed,
Even in high-speed response processing, depending on how the interrupt order is initially set, it is possible to take into account the frequency of interrupts, the priority of processing, etc., and it is effective in enabling efficient execution of the ladder.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の一実施例を示すブロック図、第2図
は第1図の動作を説明した模式図である。 100・・・制御信号入出力部、200・・・割込み条
件判定部、300・・・割込み番地発生部、400・・
・ラダーシーケンス制御部、401・・・高速割込み制
御部、402・・・繰り返し制御部、403・・・入出
力信号制御部。
FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a schematic diagram explaining the operation of FIG. 1. 100... Control signal input/output section, 200... Interrupt condition determination section, 300... Interrupt address generation section, 400...
- Ladder sequence control unit, 401... High speed interrupt control unit, 402... Repetition control unit, 403... Input/output signal control unit.

Claims (1)

【特許請求の範囲】 1、ラダー図でプログラミングするラダーシーケンサの
高速割込み型制御方法において、制御対象の作業を2つ
に分類し、1つは通常の繰り返し処理を実行し、又もう
1つは高速割込みの条件判定部とその割込み処理番地発
生部により起動される高速割込み処理とを並行して実行
することを特徴とするシーケンサの高速割込み型制御方
法。 2、繰り返し処理を実行する繰り返し制御部と、制御対
象入力信号を確認し、高速応答を行うか否かの判定を行
うと共に割込み処理番地を発生させその処理を実行する
高速割込み制御部とを含むことを特徴とするシーケンサ
の高速割込み型制御装置。
[Claims] 1. In a high-speed interrupt type control method for a ladder sequencer that is programmed using a ladder diagram, the work to be controlled is divided into two, one for performing normal repetitive processing, and the other for performing normal repetitive processing. A high-speed interrupt type control method for a sequencer, characterized in that a high-speed interrupt condition determination section and a high-speed interrupt processing activated by the interrupt processing address generation section are executed in parallel. 2. Includes a repetition control unit that executes repetitive processing, and a high-speed interrupt control unit that checks the input signal to be controlled, determines whether or not to perform a high-speed response, generates an interrupt processing address, and executes the processing. A high-speed interrupt type control device for a sequencer, which is characterized by:
JP16703490A 1990-06-26 1990-06-26 Method and device for high speed interruption type control of sequencer Pending JPH0455906A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16703490A JPH0455906A (en) 1990-06-26 1990-06-26 Method and device for high speed interruption type control of sequencer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16703490A JPH0455906A (en) 1990-06-26 1990-06-26 Method and device for high speed interruption type control of sequencer

Publications (1)

Publication Number Publication Date
JPH0455906A true JPH0455906A (en) 1992-02-24

Family

ID=15842162

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16703490A Pending JPH0455906A (en) 1990-06-26 1990-06-26 Method and device for high speed interruption type control of sequencer

Country Status (1)

Country Link
JP (1) JPH0455906A (en)

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