JPH0455957A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain the ring address processing at a high speed even in the external extension by performing the automatic ring address processing just by applying the start regardless of the address processing. CONSTITUTION:An output signal 112 of a pointer selection 110 showing the value of a start pointer 108 reads out the pointer designated by a ROM and writes the value into a current pointer 101, a limit pointer 102, and an initial pointer 103. The output of the pointer 101 serves as an address signal 104. Finally the addresses are added together by an adder 105 and compared with the value of the pointer 102 by a comparator 106. If the match is secured in this comparison, a multiplexer 107 is switched and the value of the pointer 103 is written into a RAM 113. Thereafter a series of these operations are repeated at each reception of a start signal. Thus the ring address processing is carried out at a high speed even in the external extension.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated circuit that realizes automatic ring addressing in a digital signal processing LSI, particularly a processor type LSI.

2. Prior Art FIG. 2 shows an example of an address generation circuit in a conventional semiconductor integrated circuit. 200 is an instruction decoder;
201 is an output selection signal, 202 is a write selection signal, 20
3 is a demultiplexer, 204 is a multiplexer, 20
5 and 209 are address signals, 206 is an output latch circuit,
207 is an address output, 208 is an adder, 210 is an addition signal, and 211 is a register group.

The operation of the address generation circuit configured as above will be explained. First, the instruction decoder 200 decodes the instruction and determines which register group 211 is to be read. One selected address is output from the multiplexer 204 and then latched by the output latch circuit 206. Then, the output 207 of the output latch circuit 206 becomes valid as an address output. After that, it is incremented by the adder 208, and again by the instruction decoder to the demultiplexer 203.
Rewriting to the register group 211 is performed via the .

By the way, one method of implementing ring addressing, which is often used in digital signal processing, is to use the above-mentioned circuit and perform it by software. In other words, it compares whether it is a ring end or not, and if it matches, it loads the initial. All of these processes are executed by software. Another method is to realize a ring address by adding a comparator and a multiplexer to the address circuit.

Problems to be Solved by the Invention However, achieving this with software requires a large number of cycles, which is a problem in digital signal processing where real-time processing is important.Also, in method 2, are mostly hardened, but must be decoded by an instruction decoder, which means the user has to specify which register to select and whether to increment or not. Especially for external extensions where speed is an issue. In this case, the decoding time becomes a speed bottleneck.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit that can automatically implement ring addressing without decoding instructions.

Means for Solving the Problems A semiconductor integrated circuit according to the present invention includes a register indicating a plurality of current addresses, a register indicating the start and end of a ring, a comparator, an adder, and a built-in sequencer. This system automatically performs ring address processing only by starting the ring address processing without any involvement in the address processing.

Operation The present invention can perform ring address processing at high speed even in the case of external expansion due to the above-described configuration.

Embodiment FIG. 1 shows the configuration of an address circuit of a semiconductor integrated circuit in an embodiment of the present invention. 10 in Figure 1
0 is a bus, 101 is a current pointer, 102 is a limit pointer, 103 is an initial pointer, 104 is an address output, 105 is an adder, 106 is a comparator, 107
is a multiplexer, 108 is a start pointer, 109
is the end pointer, 110 is the pointer selection counter, 1
11 is a comparator, and 112 is a pointer selection signal. Note that 113 is a RAM.

The operation of the address circuit of this embodiment configured as described above will be explained below.

First, the current value of each pointer is stored in the RAM 113.

Write limit value and initial value. Next, the start pointer 108 is written to indicate which pointer to use, and the end pointer 109 is written to indicate which pointer to use. Pointer selection is performed by a counter 110, which increments the value of the start pointer 108 for each process, and when it matches the end pointer 109, the start pointer 108 is reloaded.

The sequencer then automatically starts operating by sending a start signal to the entire circuit. First, start point 1
The output signal 112 of the pointer selection counter 110 indicating a value of 08 reads out the pointer specified by the ROM (not shown), and the current pointer 101. Write a value to the limit pointer 102° and the initial pointer 103.

The output of the current pointer 101 is an address signal 104. Finally, the address is added by an adder 105 and compared with the value of the limit pointer 102 by a comparator 106. If they match, the multiplexer 107 is switched and the value of the initial pointer 103 is written to the RAMI 13.

A ring address can be realized by repeating this series of operations every time an activation signal is received.

As described in detail, according to the present invention, ring address processing can be automatically realized by simply sending a start signal without the need to decode instructions, and there is no speed bottleneck even when externally extended. (It is possible to operate at high speed.)

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts of a practical semiconductor integrated circuit according to the present invention, and FIG. 2 is a block diagram of main parts of a conventional semiconductor integrated circuit. 100...Bus, 101...Current pointer, 102...Limit pointer, 10
3...Initial pointer, 104...
・Address output, 105...Adder, 106・
... Comparator, 107 ... Multiplexer, 108 ... Start pointer, 109 ...
... End pointer, 110 ... Pointer selection counter, 111 ... Comparator, 112 ...
...Pointer selection signal, 113...RAM.

Claims (1)

[Claims] It is equipped with registers that indicate multiple current addresses, registers that indicate the start and end of the ring, a comparator, and an adder, as well as a built-in sequencer, so that it can only be activated without being involved in address processing. A semiconductor integrated circuit characterized by automatically performing ring address processing.