JPH0456260A - Semiconductor device lead frame - Google Patents

Semiconductor device lead frame

Info

Publication number
JPH0456260A
JPH0456260A JP2167200A JP16720090A JPH0456260A JP H0456260 A JPH0456260 A JP H0456260A JP 2167200 A JP2167200 A JP 2167200A JP 16720090 A JP16720090 A JP 16720090A JP H0456260 A JPH0456260 A JP H0456260A
Authority
JP
Japan
Prior art keywords
semiconductor chip
die pad
lead frame
semiconductor device
groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2167200A
Other languages
Japanese (ja)
Inventor
Yoshitaka Hasegawa
義孝 長谷川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP2167200A priority Critical patent/JPH0456260A/en
Publication of JPH0456260A publication Critical patent/JPH0456260A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01308—Manufacture or treatment of die-attach connectors using permanent auxiliary members, e.g. using alignment marks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07141—Means for applying energy, e.g. ovens or lasers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To prevent adhesive agent or a molten Au-Si layer from flowing out of a die pad and attaching to the side face of a semiconductor chip by a method wherein a groove is provided to the part of a die pad outside the semiconductor chip or a suspension lead. CONSTITUTION:A groove 9 is provided to the part of a die pad 2 mounted with a semiconductor chip 5 outside the semiconductor chip or a suspension lead 3. By this setup, for instance when a load or a scrubbing operation is given to the semiconductor chip 5 with a pyramidal collet 7, adhesive agent 6 or molten Au-Si layer is made to flow into the groove 9. Therefore, the excessive adhesive agent 6 or the molten Au-Si layer is prevented from flowing out of the die pad 2 and attaching to the side face of the semiconductor chip 5, so that a semiconductor device can be improved in reliability. Furthermore, inner leads can be provided adjacent to a die pad, as a result a semiconductor device can deal with micronization and large-scale integration.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置用リードフレームに関し、特にグイ
パッド面の半導体チップより外側もしくは吊りリードに
溝を設け、グイボンド時の接着剤またはＡｕ−５ｉ溶融
層の流出を防止し、半導体チップ側面の付着を抑えるも
のである。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to lead frames for semiconductor devices, and in particular, grooves are provided on the outside of the semiconductor chip on the pad surface or on the hanging leads to prevent the adhesive or Au-5i melt layer from forming when bonding. This prevents leakage and suppresses adhesion to the side surfaces of semiconductor chips.

従来の技術 近年、半導体素子の微細化および大集積化が進み、チッ
プサイズもパッケージの限界まで大きく配置されている
。BACKGROUND OF THE INVENTION In recent years, semiconductor devices have become smaller and more highly integrated, and chip sizes are being increased to the limits of packages.

以下に従来のグイボンド済みのリードフレームおよび代
表的なグイボンド方法について第３図（ａ）、　（ｂｌ
を参照して説明する。The conventional Gui-bonded lead frame and the typical Gui-bond method are shown below in Figure 3 (a) and
Explain with reference to.

第３図（ａ）において周辺部にリードフレーム１が設け
られ、その中央部には半導体チップを搭載するダイパッ
ド２が、このダイパッドから側方に延びる吊りリード３
を介してリードフレームの外枠に固定接続され、また、
半導体チップと金属の細線で接続されるインナーリード
４がある。次にグイボンド方法として、第３図（ｂｌに
示すように半導体チップ５を搭載するダイパッド２の上
に、接着剤６が塗布され、角錐コレット７により真空８
で吸着された半導体チップ５は、ダイパッド２および接
着剤６の上で荷重およびスクラブ動作を加えてグイボン
ドされる。しかし、接着剤を使用しなくて、加熱による
加重、またはスクラブ動作を加え、グイボンドする方法
もある。In FIG. 3(a), a lead frame 1 is provided at the periphery, a die pad 2 on which a semiconductor chip is mounted is mounted at the center of the lead frame 1, and suspension leads 3 extending laterally from the die pad.
It is fixedly connected to the outer frame of the lead frame through the
There is an inner lead 4 connected to the semiconductor chip by a thin metal wire. Next, as shown in FIG. 3 (bl), an adhesive 6 is applied onto the die pad 2 on which the semiconductor chip 5 is mounted, and a pyramidal collet 7 is used to apply a vacuum 8.
The semiconductor chip 5 adsorbed is bonded onto the die pad 2 and the adhesive 6 by applying a load and a scrubbing action. However, there is also a method of bonding without using an adhesive by applying heat or scrubbing.

発明が解決しようとする課題 しかし、上記従来の構成では角錐コレット７により真空
８で吸着された半導体チップ５を接着剤６が塗布された
ダイパッド２に、荷重またはスクラブ動作を加えた場合
、接着剤６の量、角錐コレット７への荷重、またはスク
ラブ回数など、様様な条件によって接着剤６がグイパッ
ド２から流出し、インナーリード４へ接触したり、角錐
コレット７の先端に付着し半導体チップ表面へも付着す
る場合がある。Problems to be Solved by the Invention However, in the above-mentioned conventional configuration, when a load or a scrubbing operation is applied to the semiconductor chip 5 which has been vacuum-adsorbed by the pyramidal collet 7 to the die pad 2 coated with the adhesive 6, the adhesive Depending on various conditions such as the amount of adhesive 6, the load on the pyramidal collet 7, or the number of times of scrubbing, the adhesive 6 may flow out of the goo pad 2 and come into contact with the inner lead 4, or adhere to the tip of the pyramidal collet 7 and reach the surface of the semiconductor chip. may also adhere.

第４図は、グイボードとして角錐コレット７により真空
８で吸着された半導体チップ５を接着剤６が塗布された
グイパッド２に、荷重およびスクラブ動作を加えた時、
接着剤６がインナーリードードに接触および、半導体チ
ップ５側面に付着した様子を示す。また、矢印Ａは角錐
コレット７の動きの様子を示す。FIG. 4 shows that when a semiconductor chip 5, which is vacuum-adsorbed by a pyramidal collet 7 as a goo board, is applied to a goo pad 2 coated with an adhesive 6, a load and a scrubbing action are applied.
The adhesive 6 is shown coming into contact with the inner lead electrode and adhering to the side surface of the semiconductor chip 5. Further, arrow A indicates the movement of the pyramidal collet 7.

このようにして、接着剤６がインナーリード４に接触し
た場合特性不良となり、また、半導体チップ５表面に付
着した場合、アルミニウム腐食など、信頼性に悪影響を
およぼす。また、微細化および大集積化により半導体チ
ップとダイパッドの大きさが同等であったり、ダイパッ
ドとインナーリードまでの距離が狭くなるにつれて、よ
り一層大きな問題となってきた。In this way, if the adhesive 6 comes into contact with the inner lead 4, it will cause poor characteristics, and if it adheres to the surface of the semiconductor chip 5, it will cause aluminum corrosion, which will adversely affect reliability. Furthermore, as miniaturization and large-scale integration have resulted in semiconductor chips and die pads becoming equal in size, and as the distance between the die pad and inner leads becoming narrower, this problem has become even more serious.

本発明は上記従来の問題を解決するもので、ダイパッド
は半導体チップより外側もしくは吊りリードに溝を設け
て、グイボンド時の接着剤またはＡｕ−５ｉ溶融層をダ
イパッドより外への流出を防止し、およびチップ側面の
付着を抑えることのできる、信頼性の高い半導体装置用
リードフレームを提供することを目的とするものである
。The present invention solves the above-mentioned conventional problem, and the die pad is provided with a groove on the outside of the semiconductor chip or on the hanging lead to prevent the adhesive or the Au-5i molten layer from flowing out of the die pad when bonding. Another object of the present invention is to provide a highly reliable lead frame for a semiconductor device that can suppress adhesion on the side surface of a chip.

課題を解決するための手段 上記課題を解決するために、本発明の半導体装置用リー
ドフレームは、半導体チップを搭載するダイパッドの半
導体チップより外側または、吊りリードに溝を設けたも
のである。Means for Solving the Problems In order to solve the above problems, the lead frame for a semiconductor device of the present invention is provided with a groove on the outside of the semiconductor chip of the die pad on which the semiconductor chip is mounted, or on the suspension lead.

作用 上記構成により、ダイパッドの半導体チップより外側、
または吊りリードに溝を設けているため、グイボンド時
に荷重、スクラブ動作を加えても接着剤またはＡｕ−５
ｉ溶融層がダイパッドより外に流出もしくは、チップ表
面への付着が生じることはない。したがって、半導体装
置の信頼性が向上するとともに、半導体チップとグイパ
ッドサイズが、同等寸法で設計することができ、またイ
ンナーリードもダイパッドに接近配置が可能となり、微
細化および大集積化に対応可能となる。Effect With the above configuration, the area outside the semiconductor chip of the die pad,
Or, since the hanging lead has a groove, even if a load or scrubbing action is applied during Guibonding, the adhesive or Au-5
i The molten layer does not flow out of the die pad or adhere to the chip surface. Therefore, the reliability of the semiconductor device is improved, the semiconductor chip and the guide pad size can be designed to have the same dimensions, and the inner leads can also be placed close to the die pad, making it possible to respond to miniaturization and large scale integration. becomes.

実施例 以下、本発明の一実施例について、図面を参照しながら
説明する。第１図（ａ）および（ｂｌは、本発明の一実
施例における半導体装置用リードフレームの一部を示す
正面図およびＤ−Ｄ’断面図である。EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings. FIGS. 1A and 1B are a front view and a cross-sectional view taken along line DD' of a lead frame for a semiconductor device according to an embodiment of the present invention.

周辺にリードフレーム１が設けられその中央に、半導体
チップを搭載するグイパッド２がありダイパッドは側方
に延びる吊りリード３を介してリードフレームの外枠に
固定接続されている。また半導体チップと外部端子を金
属の細線で接続するインナーリード４があり、そしてダ
イパッド９もしくは吊りリード３に接着剤の流出、半導
体チップ表面への付着を抑えるための溝９が設けられて
いる。なお、溝９はダイパッドおよび吊りリードのうち
、少なくとも一方を設けたもので、溝の寸法１位置、形
状はグイパッドサイズ、半導体チップ寸法、パッケージ
の大きさにより任意である。A lead frame 1 is provided around the periphery, and a die pad 2 on which a semiconductor chip is mounted is provided in the center thereof, and the die pad is fixedly connected to the outer frame of the lead frame via hanging leads 3 extending laterally. In addition, there is an inner lead 4 that connects the semiconductor chip and an external terminal with a thin metal wire, and a groove 9 is provided in the die pad 9 or the hanging lead 3 to prevent adhesive from flowing out or adhering to the surface of the semiconductor chip. Note that the groove 9 is provided with at least one of a die pad and a hanging lead, and the size and position of the groove and the shape are arbitrary depending on the size of the die pad, the size of the semiconductor chip, and the size of the package.

本実施例のリードフレームによる作用について、以下に
説明する。The effect of the lead frame of this embodiment will be explained below.

第２図は接着剤または、Ａｕ−５ｉ溶融層の流出および
チップ表面の付着を抑えるための溝９を備えてグイボン
ドする際の角錐コレット７による半導体チップ５をスク
ラブ動作する様子を示した図である。ここで矢印Ａは角
錐コレット７の動きを示す。角錐コレット７で半導体チ
ップ５を荷重およびスクラブ動作すると、接着剤または
Ａｕ−８ｉ溶融層は溝９に入る。したがって、グイボン
ド時の過剰な接着剤、もしくはＡｕ−３ｉ溶融層はダイ
パッドの外へ流出することはない。また、チップ側面へ
の付着を抑えることもできる。このようにダイパッドの
外へ流出しないため、インナーリード４はグイパッド２
に接近配置することができる。FIG. 2 is a diagram showing the scrubbing operation of the semiconductor chip 5 by the pyramidal collet 7 when bonding with grooves 9 to suppress the outflow of the adhesive or the Au-5i molten layer and the adhesion of the chip surface. be. Here, arrow A indicates the movement of the pyramidal collet 7. When the pyramid collet 7 loads and scrubs the semiconductor chip 5, the adhesive or the Au-8i melt layer enters the groove 9. Therefore, excess adhesive or Au-3i melt layer during bonding will not flow out of the die pad. It is also possible to suppress adhesion to the side surfaces of the chip. In this way, the inner leads 4 are connected to the die pad 2 so that they do not leak out of the die pad.
can be placed close to each other.

発明の効果 以上のように、本発明の半導体装置用リードフレームに
よれば、グイパッドは半導体チップより外側でもしくは
吊りリードに溝を設けることによって、グイボンドする
際に接着剤、もしくはＡｕ−８ｉ溶融層のグイパッドよ
り外へ流出を防ぎ、またチップ側面の付着を抑えること
ができ、半導体装置の信頼性を向上させることができる
とともに、微細化および大集積化に対応することができ
るものである。Effects of the Invention As described above, according to the lead frame for a semiconductor device of the present invention, the Gui pad is provided with a groove on the outside of the semiconductor chip or in the suspension lead, so that when Gui bonding is performed, adhesive or Au-8i fused layer is used. It is possible to prevent the liquid from flowing out from the goo pad and to suppress adhesion to the side surface of the chip, thereby improving the reliability of the semiconductor device and making it possible to respond to miniaturization and large-scale integration.

【図面の簡単な説明】[Brief explanation of drawings]

本発明の一実施例における半導体装置用リードフレーム
を示す正面図、およびその要部断面図、第２図は同半導
体装置用リードフレームの利用工程における要部断面図
、第３図は従来の半導体装置用リードフレームの正面図
、およびその利用工程における要部断面図、第４図は同
半導体装置用リードフレームのグイボンド状態を示す断
面図である。 １・・・・・・リードフレーム、２・・・・・・グイパ
ット、３・・・・・・吊りリード、４・・・・・・イン
ナーリード、５・・・粗生導体チップ、６・・・・・・
接着剤、７・・・・・・角錐コレット、８・・・・・・
真空、９・・・溝。A front view showing a lead frame for a semiconductor device according to an embodiment of the present invention, and a cross-sectional view of the main part thereof, FIG. 2 is a cross-sectional view of the main part in the process of using the lead frame for a semiconductor device, and FIG. FIG. 4 is a front view of the lead frame for a device, a cross-sectional view of a main part in the process of using the lead frame, and a cross-sectional view showing the lead frame for a semiconductor device in a bonded state. DESCRIPTION OF SYMBOLS 1...Lead frame, 2...Gui pad, 3...Hanging lead, 4...Inner lead, 5...Rough conductor chip, 6...・・・・・・
Adhesive, 7...Pyramid collet, 8...
Vacuum, 9...grooves.

Claims (1)

【特許請求の範囲】[Claims] 　半導体チップを搭載するダイパッドの前記半導体チッ
プより外側、もしくは吊りリードに溝を設けた半導体装
置用リードフレーム。A lead frame for a semiconductor device in which a groove is provided on a die pad on which a semiconductor chip is mounted, on the outside of the semiconductor chip, or on a hanging lead.
JP2167200A 1990-06-25 1990-06-25 Semiconductor device lead frame Pending JPH0456260A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2167200A JPH0456260A (en) 1990-06-25 1990-06-25 Semiconductor device lead frame

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2167200A JPH0456260A (en) 1990-06-25 1990-06-25 Semiconductor device lead frame

Publications (1)

Publication Number Publication Date
JPH0456260A true JPH0456260A (en) 1992-02-24

Family

ID=15845283

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2167200A Pending JPH0456260A (en) 1990-06-25 1990-06-25 Semiconductor device lead frame

Country Status (1)

Country Link
JP (1) JPH0456260A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007012857A (en) * 2005-06-30 2007-01-18 Renesas Technology Corp Semiconductor device
JP2013219194A (en) * 2012-04-09 2013-10-24 Sansha Electric Mfg Co Ltd Semiconductor device
JP2016105508A (en) * 2016-02-29 2016-06-09 株式会社三社電機製作所 Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007012857A (en) * 2005-06-30 2007-01-18 Renesas Technology Corp Semiconductor device
JP2013219194A (en) * 2012-04-09 2013-10-24 Sansha Electric Mfg Co Ltd Semiconductor device
JP2016105508A (en) * 2016-02-29 2016-06-09 株式会社三社電機製作所 Semiconductor device

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