JPH0456323A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To eliminate the need for the formation of a plasma oxide film and etching back, simplify process, and enhance the degree of evenness by depositing a plasma TEOS oxide film after having carried out a first layer wiring by way of an insulation oxide film formed in a semiconductor substrate, reacting organic silane with O3 based on a normal pressure CVD process, depositing the TEOS-O3 oxide film, and flattening an interlaminar insulation film. CONSTITUTION:An insulation oxide film 12 is formed on a silicon substrate 11 where a first layer Al wiring is formed thereon. A TEOS oxide film 14, which is accurate and an excellent insulator, is further deposited as a sub-layer film for an interlaminar insulation film. Then, based on the application of normal pressure CVD, TEOS, which is organic silane, is arranged to react with O3, thereby forming a TEOS-O3 oxide film 15 and further flattening the film. The normal pressure TEOS-O3 oxide film 15 is capable of forming a more accurate film than the vacuum TEOS-O3 oxide film, which makes it possible to provide more excellent insulating properties and deposit the film until it is flattened to a satisfactory extent. Then, after having formed a through hole, a second layer Al wiring 16 is carried out. Finally, a plasma SiN film 17 is deposited as a passivation film.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention provides a method for flattening an interlayer insulating film of a semiconductor element.
The present invention relates to a semiconductor device manufacturing method in which a writing pressure TEOS (tetraethyl orthosilane)-〇 oxide film is used after a plasma oxide film is deposited.

(Conventional technology) Monthly/Semiconductor World, 5elIltc
A conventional method for manufacturing a semiconductor device for planarizing an interlayer insulating film, which is described in "Onductor World 1989.10", will be sequentially explained with reference to FIG.

As shown in FIG. 2(a), after forming a silicon oxide film 22 on a silicon substrate 21, a first layer of N wiring 23 is formed.

Next, as shown in FIG. 2(b), plasma TE is applied to the entire surface.
A silicon oxide film 24 is deposited on M by OS-CVD.

Next, as shown in FIG. 2(C), the reduced pressure TEOSo3-
A CVD oxide film 25 is used to fill the narrow space.

Next, as shown in FIG. 2(d), the plasma TEO
An oxide film 26 is deposited by S-CVD.

Next, as shown in FIG. 2(e), the thickness of the insulating film 26 is adjusted by etching back using RIH.

Next, as shown in Figure 2), after forming through-holes and a second layer of N wiring 27, plasma-3iN2B, which is a passivation film, is deposited.

(Problem to be solved by the invention) However, in the semiconductor device manufacturing method described above,
Etching back using RIB is required for planarization, which not only increases the number of steps, but also causes problems such as difficulty in controlling the etched film thickness and deterioration of uniformity due to etching and etchback.

Furthermore, the insulation properties of the oxide film in reduced pressure TEOS-0 are poor;
Furthermore, since cracks are likely to occur, it is difficult to deposit a film with a thickness of 5000 Å or more.

In addition, in flattening, depending on the step space width,
There will be parts that you are not satisfied with.

This invention solves the problems of the above-mentioned prior art, such as difficulty in controlling etchback during planarization of the interlayer insulating film, and poor insulation properties.
The present invention provides a semiconductor device manufacturing method that solves the problem that it is difficult to increase the thickness of llyL.

(Means for Solving the Problems) In order to solve the above-mentioned problems, the present invention provides a semiconductor device manufacturing method in which plasma TE is applied after forming the first layer of wiring.
Atmospheric pressure TEO by depositing a plasma oxide film such as O5 oxide film
This method introduces a planarization process using an S-03 oxide film.

(Function) According to the present invention, since the above steps are introduced in the semiconductor device manufacturing method, a plasma oxide film with excellent insulating properties and a plasma oxide film with excellent insulating properties and a relatively dense and good insulating film that can be easily flattened are formed. Since the interlayer insulating film is formed in combination with the atmospheric pressure TEOS-O3 oxide film, the formation of the upper plasma oxide film and the etch-back process are omitted, and the flatness is improved. Problems can be removed.

(Example) Hereinafter, an example of the semiconductor device manufacturing method of the present invention will be described based on the drawings. Figures 1(a) to 1(e)
) is a process cross-sectional view of one embodiment. Although the material of the multilayer wiring does not matter in the embodiment of FIG. 1, M wiring will be used as an example for explanation.

First, as shown in FIG. 1(a), an insulating oxide film 12 is formed on a silicon substrate as a semiconductor substrate, and a first layer M wiring 13 is formed on this insulating film 12.

Next, as shown in FIG. 1 et al., a plasma TEOS oxide film having a dense film and good insulating properties is deposited as a lower layer film of the interlayer insulating film.

Next, as shown in FIG. 1(C), TEOS as an organic silane is reacted with O8 using a normal pressure CVD method to form TE.
An OS-O3 oxide film is formed and planarized at about 400° C. with a flow rate ratio of Ol and TEOS of 10 or more.

The normal pressure TEOS-03 oxide film can form a denser film than the reduced pressure TEOS-○ oxide film, has better insulation, and does not generate cracks even when deposited up to 2n.

Therefore, the film can be deposited until it is sufficiently planarized.

Next, as shown in FIG. 1(d), after forming through holes, the second layer M wiring 16 is formed.

Finally, as shown in Figure 1(e), plasma SiNM
17 is deposited as a Bassibasigon film.

(Effects of the Invention) As described above, according to the semiconductor device manufacturing method of the present invention, a plasma oxide film with excellent insulating properties, a normal pressure TEOS-03 oxide film with excellent planarization, and a relatively dense and good insulating property can be obtained. Since the interlayer insulating layer is formed by combining the two films, the process of forming the upper layer plasma oxide film and etching back, which are performed when using the reduced pressure TEOS-03 oxide film, is unnecessary, simplifying the process and improving flatness. It is possible to improve the degree of

[Brief explanation of drawings]

FIGS. 1(a) to 1(e) are process cross-sectional views of an embodiment of the semiconductor device manufacturing method of the present invention, and FIGS. 2IN(a) to 2(f) are process sectional views of an embodiment of the semiconductor device manufacturing method of the present invention. It is a process sectional view. 11... Silicon substrate, 12... Insulating oxide film, 13
...First layer M wiring, 14...Plasma TEOS oxide film, 15...TEOS-o, oxide film, 16...2
Layer M wiring, 17... plasma SiN film. 16: Second layer At wiring 14: Plasma TEO5 oxide film 17: Plasma SiN film Process sectional view of the present invention Figure 26: E-oxide film 23; First layer A wiring (a) 24: Silicon oxide film Plasma SiNM conventional process cross-sectional diagram

Claims (1)

[Claims] (a) A step of depositing a plasma TEOS oxide film as a lower layer film of an interlayer insulating film after forming a first layer of wiring via an insulating oxide film formed on a semiconductor substrate; (b) ) A method for manufacturing a semiconductor device, comprising the steps of: depositing a TEOS-O_3 oxide film by reacting organic silane and O_3 by an atmospheric pressure CVD method, and planarizing the interlayer insulating film.