JPH04563A - Simulation system for input/output common pin - Google Patents
Simulation system for input/output common pinInfo
- Publication number
- JPH04563A JPH04563A JP2100591A JP10059190A JPH04563A JP H04563 A JPH04563 A JP H04563A JP 2100591 A JP2100591 A JP 2100591A JP 10059190 A JP10059190 A JP 10059190A JP H04563 A JPH04563 A JP H04563A
- Authority
- JP
- Japan
- Prior art keywords
- input
- output
- pin
- output pin
- wired
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims description 7
- 230000000644 propagated effect Effects 0.000 abstract description 7
- 238000011156 evaluation Methods 0.000 abstract description 5
- 238000012545 processing Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000002457 bidirectional effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000012795 verification Methods 0.000 description 1
Landscapes
- Test And Diagnosis Of Digital Computers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は論理シミュレーションに関し、特に入出力兼用
ピンを含む論理シミュレーションに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic simulation, and particularly to logic simulation including input/output pins.
半導体技術の進歩に従い、ＬＳＩの規模が増大し、その
応用分野も急激に広がりつつある。また、ＬＳＩの製造
形態も少品種多量生産から多品種少量生産へと移行し、
製品のライフサイクルも短かくなりつつある。これに伴
い、以前にも増して必要な機能を早くかつ正しく実現で
きる設計支援システムが必要不可欠となってきている。BACKGROUND OF THE INVENTION As semiconductor technology advances, the scale of LSIs is increasing and the fields of their application are rapidly expanding. Additionally, the manufacturing format of LSIs has shifted from high-volume production of small variety to high-mix low-volume production.
Product life cycles are also becoming shorter. Along with this, design support systems that can quickly and correctly implement necessary functions are becoming more essential than ever.
このため、実際のＬＳＩを製造する前に論理、タイミン
グ検証を実行する論理シミュレータが開発され活用され
ている。For this reason, logic simulators that perform logic and timing verification before manufacturing an actual LSI have been developed and utilized.
初期の論理シミュレータは信号の流れる方向が一方向で
ある単方向素子のみをシミュレーション対象としていた
が、最近ではＭＯＳ回路技術の発達に伴い信号の流れる
方向が特定できない双方向素子（ＭＯＳスイッチ等）を
含む回路の正確な論理シミュレーションが要求されてい
る。Early logic simulators only simulated unidirectional elements in which the signal flow direction is one direction, but with the recent development of MOS circuit technology, it is now possible to simulate bidirectional elements (such as MOS switches) in which the signal flow direction cannot be specified. Accurate logic simulation of the circuits involved is required.
従来の入出力兼用ピンシミュレーション方式はピンを入
力部と出力部に分割せず、状態値としては入出力状態値
のみをもち、入出力兼用ピンにファンアウトしている全
ての論理素子の出力を入力とし、入出力兼用ピンからフ
ァンアウト−している全ての論理素子の入力部へ状態値
を伝搬する。The conventional input/output pin simulation method does not divide pins into input and output parts, has only input/output state values, and outputs of all logic elements fanned out to input/output pins. It is used as an input, and the state value is propagated from the input/output pin to the input parts of all fan-out logic elements.
上述した従来の入出力兼用ピンシミュレーション方式は
、シミュレーション結果の正当性を保証するため、入出
力兼用ピンにファンアウトしている論理素子から入出力
兼用ピンからファンアウトしている論理素子へ状態値を
伝搬するためには必ず入出力兼用ピンの入出力状態値を
継歯しなければならないので、むだな評価を必要とする
。また、入出力兼用ピンの入出力状態値は入出力兼用ピ
ンの属する論理素子の出力状態値と入出力兼用ピンにフ
ァンアウトしている全ての論理素子の出力状態値のワイ
ヤード演算を行なった値を格納しなければならないので
、入出力兼用ピンの属する論理素子の出力状態値を観測
できない。さらに入出力兼用ピン同志が接続された場合
、シミュレーション上の接続情報が複雑になり、シミュ
レーションに多大な時間を要するという欠点があった。In the conventional input/output pin simulation method described above, in order to guarantee the validity of simulation results, the state value is transferred from the logic element that is fanned out to the input/output pin to the logic element that is fanned out from the input/output pin. In order to propagate the input/output pin, the input/output state value of the input/output pin must be relayed, which requires wasteful evaluation. In addition, the input/output state value of the input/output pin is the value obtained by performing a wired operation of the output state value of the logic element to which the input/output pin belongs and the output state values of all the logic elements fanned out to the input/output pin. must be stored, the output state value of the logic element to which the input/output pin belongs cannot be observed. Furthermore, when the input/output pins are connected, the connection information in the simulation becomes complicated and the simulation takes a lot of time.
本発明の入出力兼用ビンシミュレーション方式は、入出
力兼用ピンを入力部と出力部に分割する入出力分離手段
と、前記入出力兼用ピンにファンアウトしている論理素
子群の出力と前記入出力兼用ピンの前記出力のワイヤー
ド演算を行い、演算結果を前記入出力兼用ピンの前記入
力部と前記入出力兼用ピンからファンアウトしている論
理素子群ノ入力部へ接続するワイヤード素子を生成する
ワイヤード生成手段とを含むようにして構成される。The input/output bin simulation method of the present invention includes an input/output separation means that divides the input/output pin into an input part and an output part, and an output of a logic element group that is fanned out to the input/output pin and the input/output pin. A wired element that performs a wired operation on the output of the dual-purpose pin and connects the operation result to the input part of the input/output pin and the input part of the logic element group fanned out from the input/output pin. and generating means.
次に、本発明の実施例について図面を参照して詳細に説
明する。Next, embodiments of the present invention will be described in detail with reference to the drawings.
第１図は本発明の入出力兼用ビンシミュレーション方式
の第一の実施例を示す説明図である。同図において１は
論理素子、２は入出力兼用ピン。FIG. 1 is an explanatory diagram showing a first embodiment of the input/output bin simulation method of the present invention. In the figure, 1 is a logic element, and 2 is an input/output pin.
３は入出力兼用ピン入力部、４は入出力兼用ピン出力部
、５はワイヤード素子である。本発明によれば同図（ａ
）に示すような回路は同図（ｂ）のようにモデル化され
る。3 is an input/output pin input section, 4 is an input/output pin output section, and 5 is a wired element. According to the present invention, the same figure (a
) is modeled as shown in FIG. 3(b).
入出力兼用ピンへファンアウトする論理素子群１１の出
力は入出力兼用ピン出力部４の出力と共にワイヤード演
算され、演算結果は入出力兼用ピン入力部３と入出力兼
用ピンからファンアウトする論理素子群１２とへ伝搬さ
れる。入出力兼用ピン入力部３の状態値およびその他の
ピンの状態値から論理素子１の動作を決定し、入出力兼
用ピンの状態値を入出力兼用ピン出力部４へ伝搬し、さ
らにワイヤード素子５へ伝搬する。このワイヤード素子
５の評価、入出力兼用ピン出力部３への状態値登録、論
理素子１の評価、入出力兼用ピン出力部４への状態値の
伝搬という一連の処理を、状態値が収速するまで行う。The output of the logic element group 11 that fans out to the input/output pin is wired together with the output of the input/output pin output section 4, and the operation result is transferred to the input/output pin input section 3 and the logic element group 11 that fans out from the input/output pin. It is propagated to group 12. The operation of the logic element 1 is determined from the state value of the input/output pin input section 3 and the state values of other pins, and the state value of the input/output pin is propagated to the input/output pin output section 4, and then the wired element 5 propagates to A series of processes such as evaluation of the wired element 5, registration of the state value to the input/output pin output section 3, evaluation of the logic element 1, and propagation of the state value to the input/output pin output section 4 can be performed quickly. Do it until you do.
第２図は本発明の第二の実施例を示す説明図である。同
図は入出力兼用ピン同志を接続した場合を例示しており
、２１．２２は論理素子、２３゜２４は入出力兼用ピン
、２５．２７は入出力兼用ピン入力部、２６．２８は入
出力兼用ピン出力部、２９はワイヤード素子である。本
発明によれば同図（ａ）に示す回路は同図（ｂ）のよう
にモデル化される。すなわち入出力兼用ピンにファンア
ウトする論理素子の出力と各入出力兼用ピン出力部２６
．２８とがワイヤード素子２９によってワイヤード演算
され、演算結果が各入出力兼用ピン入力部２５．２７及
び入出力兼用ピンからファンアウトしている論理素子へ
伝搬される。このような単純な接続によって入出力兼用
ピンを含む回路を正確にシミュレートする事が可能とな
る。FIG. 2 is an explanatory diagram showing a second embodiment of the present invention. The figure shows an example where input/output pins are connected together, where 21.22 is a logic element, 23.24 is an input/output pin, 25.27 is an input/output pin input section, and 26.28 is an input/output pin. The output/pin output section 29 is a wired element. According to the present invention, the circuit shown in FIG. 3(a) is modeled as shown in FIG. 2(b). In other words, the output of the logic element that fans out to the input/output pin and each input/output pin output section 26
．． 28 is subjected to a wired operation by the wired element 29, and the operation result is propagated from each input/output pin input section 25, 27 and input/output pin to the fan-out logic element. Such simple connections make it possible to accurately simulate circuits that include input/output pins.
本発明の入出力兼用ビンシミュレーション方式は、入出
力兼用ピンを入力部と出力部に分割する入出力分離手段
と、前記入出力兼用ピンにファンアウトしている論理素
子群の出力と前記入出力兼用ピンの前記出力のワイヤー
ド演算を行い、演算結果を前記入出力兼用ピンの前記入
力部と前記入出力兼用ピンからファンアウトしている論
理素子群の入力部へ接続するワイヤード素子を生成する
ワイヤード生成手段とを含み、入出力兼用ピンにファン
アウトしている論理素子から入出力兼用ピンからファン
アウトしている論理素子へ状態値を伝搬する場合、状態
値はワイヤード素子を継歯して伝搬すればよいので入出
力兼用ピンの評価が不要になり処理時間が短縮される。The input/output bin simulation method of the present invention includes an input/output separation means that divides the input/output pin into an input part and an output part, and an output of a logic element group that is fanned out to the input/output pin and the input/output pin. A wired element that performs a wired operation on the output of the dual-purpose pin and connects the operation result to the input part of the input/output pin and the input part of a logic element group fanned out from the input/output pin. When a state value is propagated from a logic element that is fanned out to the input/output pin to a logic element that is fanned out from the input/output pin, the state value is propagated through the wired element. This eliminates the need to evaluate input/output pins, reducing processing time.
また、入出力兼用ピンを入力部と出力部に分割すること
により、入出力兼用ピンの属する論理素子自体の出力状
態値を出力部に格納し観測することができる。Furthermore, by dividing the input/output pin into an input section and an output section, the output state value of the logic element itself to which the input/output pin belongs can be stored and observed in the output section.
さらに、入出力兼用ピン同志が接続された場合、１つの
ワイヤード素子を生成して入出力兼用ピンの入力部をワ
イヤード素−子の出力に、入出力兼用ピンの出力部をワ
イヤード素子の入力にそれぞれ接続することにより、入
出力兼用ピンのシミュレーションが可能となり、接続情
報を単純化できるという効果がある。Furthermore, when input/output pins are connected, one wired element is generated, the input part of the input/output pin becomes the output of the wired element, and the output part of the input/output pin becomes the input of the wired element. By connecting them, it is possible to simulate the input/output pins, and the connection information can be simplified.
Ｌ ２１，２２・・・論理素子、２，２３．２４・・
・入出力兼用ピン、３，２５．２７・・・入出力兼用ピ
ン入力部、４，２６．２８・・・入出力兼用ピン出力部
、５，２９・・・ワイヤード素子。L 21, 22...Logic element, 2, 23.24...
- Input/output pin, 3, 25.27... Input/output pin input section, 4, 26.28... Input/output pin output section, 5, 29... Wired element.
Claims (1)
手段と、前記入出力兼用ピンにファンアウトしている論
理素子群の出力と前記入出力兼用ピンの前記出力のワイ
ヤード演算を行い、演算結果を前記入出力兼用ピンの前
記入力部と前記入出力兼用ピンからファンアウトしてい
る論理素子群の入力部へ接続するワイヤード素子を生成
するワイヤード生成手段とを含む事を特徴とする入出力
兼用ピンシミュレーション方式。an input/output separating means for dividing the input/output pin into an input part and an output part; performing a wired operation on the output of the logic element group fanned out to the input/output pin and the output of the input/output pin; The input input device is characterized in that it includes wired generation means for generating a wired element that connects the operation result to the input section of the input/output pin and the input section of a logic element group fanned out from the input/output pin. Output pin simulation method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2100591A JPH04563A (en) | 1990-04-17 | 1990-04-17 | Simulation system for input/output common pin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2100591A JPH04563A (en) | 1990-04-17 | 1990-04-17 | Simulation system for input/output common pin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04563A true JPH04563A (en) | 1992-01-06 |
Family
ID=14278118
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2100591A Pending JPH04563A (en) | 1990-04-17 | 1990-04-17 | Simulation system for input/output common pin |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04563A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0704757A1 (en) | 1994-09-29 | 1996-04-03 | Konica Corporation | A silver halide photographic light sensitive material |
-
1990
- 1990-04-17 JP JP2100591A patent/JPH04563A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0704757A1 (en) | 1994-09-29 | 1996-04-03 | Konica Corporation | A silver halide photographic light sensitive material |
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