JPH0456410A - Radiation noise reduction circuit - Google Patents

Radiation noise reduction circuit

Info

Publication number
JPH0456410A
JPH0456410A JP2166496A JP16649690A JPH0456410A JP H0456410 A JPH0456410 A JP H0456410A JP 2166496 A JP2166496 A JP 2166496A JP 16649690 A JP16649690 A JP 16649690A JP H0456410 A JPH0456410 A JP H0456410A
Authority
JP
Japan
Prior art keywords
osc
output
signal line
ground
power supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2166496A
Other languages
Japanese (ja)
Inventor
Hideaki Kato
秀章 加藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Gunma Ltd
Original Assignee
NEC Gunma Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Gunma Ltd filed Critical NEC Gunma Ltd
Priority to JP2166496A priority Critical patent/JPH0456410A/en
Publication of JPH0456410A publication Critical patent/JPH0456410A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To eliminate an spurious harmonic component while minimizing the signal delay by providing a means inserting a varactor diode between a signal line and a power supply, or between a signal line and ground, or between the signal line and the power supply and also between the signal line and ground to the circuit. CONSTITUTION:When the output of an OSC is at a high level, the potential difference between the output of the OSC and a power supply Vcc is almost zero, a static capacitance of a diode 2 is maximum. When the output of the OSC is at a low level, the potential difference between the output of the OSC and ground is almost zero, a static capacitance off a diode 3 is maximum. When the output of the OSC is almost at a threshold voltage, a voltage of about Vcc/2 is applied to the diodes 2, 3 respectively. When the diodes whose static capacitance does not give any effect on a signal waveform from the OSC in this voltage state are selected, a spurious harmonic component is eliminated while minimizing the signal delay.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は輻射雑音低減回路、特に、論理回路のスイッチ
ング時に発生する高調波の輻射雑音低減回路に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a radiation noise reduction circuit, and particularly to a radiation noise reduction circuit for harmonics generated during switching of a logic circuit.

〔従来の技術〕[Conventional technology]

従来の輻射雑音低減回路は、信号線にインダクタンスと
コンデンサを組合わせたEMIフィルタを挿入し、矩形
波の持つ高調波成分を除去することにより、自装置外へ
の輻射雑音を低減していた。
Conventional radiated noise reduction circuits reduce radiated noise to the outside of the device by inserting an EMI filter that combines an inductance and a capacitor into a signal line and removing harmonic components of a rectangular wave.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の輻射雑音低減回路は、EMIフィルタの
構成部品が固定常数であるため、入力波形に対する出力
波形全体の鈍りが著しく、これが信号の遅れとなって表
われ、回路の動作マージンを少なくし、最悪の場合は正
常な動作ができなくなるという欠点があった。
In the conventional radiation noise reduction circuit described above, the components of the EMI filter are fixed constants, so the overall output waveform is significantly blunted with respect to the input waveform, and this appears as a signal delay, reducing the circuit's operating margin. However, in the worst case, normal operation may no longer be possible.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の輻射雑音低減回路は、信号線と電源間、または
前記信号線とグランド間、または前記信号線と前記電源
および前記信号線と前記グランド間に可変容量ダイオー
ドを挿入する手段を備える。
The radiation noise reduction circuit of the present invention includes means for inserting a variable capacitance diode between a signal line and a power supply, between the signal line and the ground, or between the signal line and the power supply, and between the signal line and the ground.

〔実施例〕〔Example〕

次に、本発明について図面を参照して詳細に説明する。 Next, the present invention will be explained in detail with reference to the drawings.

第1図は本発明の一実施例を示す回路図である。FIG. 1 is a circuit diagram showing one embodiment of the present invention.

第1図に示す輻射雑音低減回路は、03C1がクロック
として使用される矩形波を出力する。
The radiation noise reduction circuit shown in FIG. 1 outputs a rectangular wave using 03C1 as a clock.

08C1と電源V c cとの間に可変容量ダイオード
2が、カソードを電源Vccに接続して入っている。
A variable capacitance diode 2 is inserted between 08C1 and the power supply Vcc with its cathode connected to the power supply Vcc.

さらに、03C1の出力とグランド間に可変容量ダイオ
ード3が、アノードをグランドに接続して入っている。
Further, a variable capacitance diode 3 is inserted between the output of 03C1 and the ground with its anode connected to the ground.

次に、動作について説明する。Next, the operation will be explained.

O3Cの出力がハイレベルにあるときは、電源Vccと
の電位差がほば0となるため、可変容量ダイオード2の
静電容量は最大となり、O5C1の出力のハイレベルに
作用する。
When the output of O3C is at a high level, the potential difference with the power supply Vcc is almost 0, so the capacitance of the variable capacitance diode 2 is maximum, which acts on the high level of the output of O5C1.

逆に、0SCIの出力がローレベルにあるときは、グラ
ンドとの電位差がほばOとなるため、可変容量ダイオー
ド3の静電容量は最大となり、03CIの出力のローレ
ベルに作用する。
Conversely, when the output of 0SCI is at a low level, the potential difference with the ground is approximately O, so the capacitance of the variable capacitance diode 3 is at its maximum, which acts on the low level of the output of 03CI.

スレッシュホールド電圧付近では、可変容量ダイオード
2,3には、それぞれ、はぼV c c / 2の電圧
がかかっているが、この時の靜電容Iが03CIの信号
波形への影響を無視できるような値の可変容量ダイオー
ドを選択することにより、信号遅延を最小としながら、
不要な高調波成分を除去する。この様子を第2図に示す
Near the threshold voltage, a voltage of about Vcc/2 is applied to each of the variable capacitance diodes 2 and 3, but the static capacitance I at this time is such that the influence of 03CI on the signal waveform can be ignored. By selecting a variable capacitance diode with a value that minimizes signal delay,
Remove unnecessary harmonic components. This situation is shown in FIG.

〔発明の効果〕〔Effect of the invention〕

本発明の輻射雑音低減回路は、信号遅延を最小にしなが
ら、不要な高調波成分を除去できるという効果がある。
The radiation noise reduction circuit of the present invention has the advantage of being able to remove unnecessary harmonic components while minimizing signal delay.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図、第2図は第1
図に示す輻射雑音低減回路動作を説明するための波形図
である。 1・・・・・・08C12〜3・・・・・−可変容量ダ
イオード。 代理人 弁理士  内 原  晋
Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
FIG. 3 is a waveform diagram for explaining the operation of the radiation noise reduction circuit shown in the figure. 1...08C12~3...-Variable capacitance diode. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] 信号線と電源間、または前記信号線とグランド間、また
は前記信号線と前記電源および前記信号線と前記グラン
ド間に可変容量ダイオードを挿入する手段を備えること
を特徴とする輻射雑音低減回路。
A radiation noise reduction circuit comprising means for inserting a variable capacitance diode between a signal line and a power supply, between the signal line and the ground, or between the signal line and the power supply, and between the signal line and the ground.
JP2166496A 1990-06-25 1990-06-25 Radiation noise reduction circuit Pending JPH0456410A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2166496A JPH0456410A (en) 1990-06-25 1990-06-25 Radiation noise reduction circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2166496A JPH0456410A (en) 1990-06-25 1990-06-25 Radiation noise reduction circuit

Publications (1)

Publication Number Publication Date
JPH0456410A true JPH0456410A (en) 1992-02-24

Family

ID=15832444

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2166496A Pending JPH0456410A (en) 1990-06-25 1990-06-25 Radiation noise reduction circuit

Country Status (1)

Country Link
JP (1) JPH0456410A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005080920A (en) * 2003-09-09 2005-03-31 Key Tranding Co Ltd Resin tray, and manufacturing method thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005080920A (en) * 2003-09-09 2005-03-31 Key Tranding Co Ltd Resin tray, and manufacturing method thereof

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