JPH0456464B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor integrated circuit device (hereinafter referred to as an IC), and in particular to an integrated injection logic device (hereinafter referred to as an IC).
The present invention relates to semiconductor devices having injection logic (abbreviated as I ² L), particularly large-scale I ² L ICs.

[Background technology]

FIG. 1 shows a layout pattern previously developed by the applicant regarding I ² L, in which a gate circuit is constituted by a pair of complementary transistors. That is, a plurality of injectors 3a, 3b, . . . are arranged in parallel on the surface of one semiconductor substrate 1 via aluminum wiring 2 from a common injection terminal Inj.
A plurality of inverters (reverse direction npn transistors) 4a ₁ , 4a ₂ , . . . 4b _{1 .} . . are arranged facing each other on both sides of each injector. Another aluminum wiring 5 is formed near each inverter as shown by the broken line, and this wiring 5 connects to the common ground terminal GND.
It is becoming. However, the applicant has found that such a layout method has the following drawbacks. In other words, in I ² L IC, the number of gates has been around 80 at most, but if the number of gates is increased to a larger scale,
As the length of the aluminum wiring 2 connecting the common injector terminal (Inj.) and each injector 3a, 3b, 3c, 3d... becomes longer, the terminal Inj.
The amount of voltage drop caused by the resistance of the aluminum wiring itself and the flowing currents I ₁ and I ₂ is different between an injector located close to the injector and an injector located far away. The potential of will be different. In other words, from terminal Inj,
The farther away the injector is, the longer it takes to connect.
The length of the Al wiring is long and the voltage drop is large, resulting in an imbalance in the injection voltage for each injector. As a result, a difference occurs in the current injected into each inverter, which changes the logic level of the inverter and changes its speed and temperature characteristics, resulting in malfunctions such as timing errors and malfunctions.

[Purpose of the invention]

The purpose of the present invention is to
The purpose of this invention is to provide an I ² L structure that can uniformize the injection current in each gate and operate stably in an I ² L IC.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in an I ² L semiconductor device, a plurality of injectors having a common injection terminal are arranged on one main surface of one semiconductor substrate, an inverter is formed facing each injector, and each inverter has a common ground terminal. The wiring connecting the common injector terminal and each injector is formed in a net shape with the same impedance, or the wiring connecting each inverter and the common ground terminal is formed in a net shape with the same impedance. By making the injection current at each gate uniform,
This stabilizes the I ² L operation.

Embodiment 1 FIG. 2 is an embodiment of the present invention, and is a plan view showing a wiring form of I ² L having four rows of injectors. In the following figures, the same reference symbols are used for the same components as those of the I ² L device shown in FIG. 1 above.

As shown in FIG. 2, the aluminum wiring from the common injection terminal Inj to each injector 3a, 3b, . . . is formed in the shape of a widening net. That is, it branches from the common wiring 2a to become wirings 2a ₁ and 2a ₂ , and then branches to become wirings 2b 1 and 2a ₂ .
2b ₂ , 2b ₃ , and further branched into 2c ₁ , 2c ₂ , 2c _{3 .} . . and connected to each indexex 3a, 3b . In this way, in a net-like wiring, if the width and length of the branching wiring are equal, the resistance values of the wiring from the common injection exit terminal to each injection extension will be equal, and the common impedance of each injector 3a, 3b, etc. will be equal. The uniform current flowing into each injector becomes approximately equal, and as a result, the injector current of I ² L does not vary depending on each gate.

Furthermore, Al wiring (broken lines 5a, 5b...
) shown in ) is similarly formed into a net shape,
The current that operates each gate of I ² L can be made uniform, and the operation can be further stabilized.

FIG. 3 is a concrete example of the above embodiment, and is a layout pattern of an I ² L semiconductor device in which low-speed (77 gates) I ² L and high-speed (48 gates) I ² L are formed on one semiconductor chip. shows. As shown in the figure, a large number of bonding pads (terminals) are arranged along the periphery of the chip, and among them, Inj is the common injection terminal, and Inj is the common ground terminal.
GND1 is shown, the power supply terminal V _CC (5V) and each gate terminal Ag to Ar, Ba to Bu, etc. are shown. The common injection terminal Inj and the injectors 3a, 3b... of the low-speed gate row are connected to a net-like wiring 2a,
Connected by 2b, 2c..., common ground terminal
GND ₁ and each inverter are wired in a net 5
a, 5b...

Embodiment 2 FIG. 4 is another embodiment of the present invention, and shows a wiring form in which a net-like wiring is formed between a common injection terminal Inj and both ends of four rows of injectors. .

In the above embodiment, the problem was the voltage imbalance between the injectors 3a, 3b, 3c, etc. arranged vertically in the drawing, but in this embodiment, the inverters ( This solves the voltage imbalance in the horizontal arrangement of reverse direction transistors 4a ₁ , 4a ₂ , 4a ₃ .

That is, the net-like wirings 2a ₀ -2a ₁ -2a ₂ -2b ₁ . . . and 2
By connecting through a ₀ '-2a ₁ '-2a ₂ '..., the impedance becomes equal at any point of each injector, and the injection current at each gate is made uniform.

Although it is omitted in the figure, the wiring connected between the common ground terminal and both ends of the inverter facing each injector (both ends of the epitaxial layer that becomes the emitter) is connected in the form of a net. The operation of I 2 L can be made more uniform by forming the I ² L.

Embodiment 3 FIG. 5 shows still another embodiment of the present invention, in which the components are stacked (laminated) on one substrate.
An example of application to I ² L/IC is shown below. This stacked I ² L IC has a plurality of injector rows each in a semiconductor island region that is electrically decomposed (isolated) from one another by junction isolation or oxide film isolation on one semiconductor substrate. Each to form ² L
The wires are connected so that I ² L shifts from high potential to low potential. In the figure, the area surrounded by the chain line is the upper stage I ² L, and the same area is the lower stage I ² L.
The I ² L ground side common terminal GND ₁ is the wiring from the lower I ² L injector common terminal to each injector formed in a net shape, and the wiring between the inverter and the ground side common terminal in each I ² L. are similarly formed in a net shape, so that the injection current of the gate in each I ² L is made uniform.

Embodiment 4 Net-like wiring can be formed not only by simply changing the planar layout shape, but also by using multilayer wiring technology as shown in FIG. In the figure, 6 is a P ^- type Si substrate, 7 is an N ⁺ buried layer, and 8 is an N ^-
Epitaxial layer, 9 is the base, 10 is the injector, 11 is the collector extraction diffusion layer, 12 is Al
Wirings 13a to 13d are multilayer Al wirings.

〔effect〕

As described above in each embodiment, according to the present invention, the wiring between the common injection terminal and each injector is formed in a net shape so that the self impedance of each injector is the same, and the wiring between each inverter and the common ground terminal is By similarly forming the wiring between the two in a net shape, a common impedance is created, and non-uniformity in injection current at each gate of I ² L is eliminated, resulting in stable logic operation without timing fluctuations or malfunctions. This has the effect of improving the characteristics and reliability of products using I ² L.

Although the invention made by the present inventor has been specifically explained based on the examples above, the present invention is not limited to the above examples, and it is understood that various changes can be made without departing from the gist of the invention. Needless to say.

[Application field]

The present invention can be applied to ICs and LSIs having I ² L, and is particularly effective when the chip size increases and the number of gates increases to 80 or more.

The above explanation mainly describes the invention made by the present inventor and the field of application that is its background.
Although the I ² L IC has been described, the present invention can be applied to all cases where wiring has a common impedance in an electronic circuit.

[Brief explanation of the drawing]

FIG. 1 is a partial plan view of a chip showing a conventional I ² L layout pattern. FIG. 2 is a plan view showing an I ² L wiring layout according to an embodiment of the present invention. FIG. 3 is an embodiment of the present invention, and is an overall plan view showing the wiring layout of a semiconductor chip having high-speed I ² L and low-speed I ² L on one substrate. FIG. 4 is another embodiment of the present invention, and is a partial plan view of a chip showing a wiring layout when wiring is formed at both ends of an injector. FIG. 5 shows another embodiment of the present invention,
1 is a partial plan view of a chip showing the wiring layout of a semiconductor device having stacked I ² L; FIG. FIG. 6 is a partially enlarged sectional view of I ² L, which is still another embodiment of the present invention. 1... Semiconductor chip, 2... Wiring, 3... Injector, 4... Inverter, 5... Ground side wiring, 6... P-type semiconductor substrate, 7... N ⁺ diffusion layer,
8...N ^- epitaxial layer, 9...Base, 1
0...Injector, 11...Collector extraction diffusion layer, 12...Al electrode, 13a to 13d...Multilayer Al wiring.

Claims (1)

[Claims] 1. A semiconductor integrated circuit device comprising a plurality of integrated injection logic elements on a semiconductor substrate, in which a plurality of elongated injectors 3a, 3b, 3c each having a terminal at one end are arranged in parallel with each other. From one common wiring section 2a provided on the base to each of the terminals, a net-like wiring is constructed so that the wiring impedance from the common wiring section to each injector is approximately equal. A semiconductor integrated circuit device characterized by: