JPH0456568A - Signal processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a signal processing device, and particularly to blocking of image signals.

2. Description of the Related Art In general, image signals have a very large amount of information, so when recording or transmitting image signals, a method of reducing the amount of information by compression encoding is used as an effective means. Here, one method is to divide an image into blocks and encode each block, and orthogonal transform encoding is a typical example. Blocking when applying orthogonal transform coding to component signals in the current system will be described below.

The sampling frequency when handling component signals in the current system is: Y: fs = 13.5MHzR-Y:
fs/2=6.75MHzB-Y: f
s/2 = 6.75 MHz is standardized. Here, when considering a signal with 525 vertical lines, the number of effective pixels and the number of effective lines in one field are as shown in Table 1.

Table 1 The signal sampled as shown in Table 1 has an integer multiple of 8 in both the number of effective pixels and the number of effective lines, so it can be divided into blocks of 8 pixels x 8 lines. The numbers are shown in Table 2.

Table 2 Next, a signal processing device that performs the above-described blocking will be described using an example. FIG. 4 is a diagram showing an example of a conventional signal processing device. In FIG. 4, 1 is an input terminal, 2 is an A/D converter that converts an input signal into a digital signal, and 3 is a digital This is a block generator that divides the converted signal into blocks of (8!i elements x 8 lines); 4.
7 is a switch, and 5.6 is a memory having a capacity for 8 lines. Finally, 8 is a DCT computing unit that performs discrete cosine transformation (DCT) on the blocked signal. The operation of the conventional signal processing device will be explained below.

A signal input from a terminal 1 is converted into a digital signal by an A/D converter 2, and then blocked by a blocking device 3. Blocking is performed by sequentially writing 8 lines of data into the memory as shown in Figure 5(a), and then writing data for 8 lines into the memory as shown in Figure 5(b).
This can be achieved by reading in blocks as shown in the figure below. Here, reading and writing of the two memories 5 and 6 are switched in units of 8 lines, reading from the memory 6 is performed while writing to the memory 5, and conversely, reading from the memory 5 is performed while writing to the memory 6. Such memory selection for writing and reading is performed using switches 4 and 7.
done by. Data is output in block-by-block order from the memory selected by the switch 7, and is subjected to DCT calculation by the DCT calculation device 8.

Problems to be Solved by the Invention However, the signal processing device described above has the following problems.

The signal sampled at the above-mentioned sampling frequency can be easily calculated by (8 pixels x 8 However, if a different sampling frequency is used, for example, the color difference signal sampled at 6.75 MHz may be thinned out to reduce the sampling frequency to 3.
．． In the case of 375 MHz, the number of horizontal pixels is 180, which is not a multiple of 8.

In view of the problems of the prior art, the present invention provides a method for reducing the number of horizontal pixels to 1.
An object of the present invention is to provide a signal processing device that realizes block division corresponding to a case where the number of horizontal pixels in one block is not equal to an integral multiple.

Means for Solving the Problems The present invention provides that when dividing an image signal having (m×i+j) horizontal pixels into blocks (m>j), the image signal is divided into m pixels in the horizontal direction and n lines in the vertical direction. This signal processing device is characterized in that it has means for dividing the block into small blocks each having three pixels in the horizontal direction and n lines in the vertical direction, and means for collecting a plurality of the small blocks to form the block.

Effect of the present invention With the above-described configuration, when dividing an image signal in which the number of horizontal pixels is not equal to an integer multiple of m into blocks of (m pixels x n lines), in addition to the blocks, (j pixels x n lines)
A small block of (line) is generated, but by collecting multiple such small blocks to form a block of (m pixels x n lines), the entire screen can be made up of (m pixels x n lines).
can be divided into blocks.

Example Embodiments of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a diagram showing an embodiment of a signal processing device according to the present invention. In FIG. 1, l is the input terminal for the color difference signal, and 2 is the A/C converting the input signal into a digital signal.
D converter, 101 is a low-pass filter that performs thinning band limitation, 102 is a thinning circuit that thins out pixels every other pixel, 10
3 is a blocker, 104.108 is switch 1
05.106.107 is a memory having a capacity for 8 lines. Further, 109 is a DCT computing unit. The operation of this embodiment will be explained below.

A color difference signal input from a terminal 1 is converted into a digital signal by an A/D converter 2 at a sampling frequency of 6.75 MHz. Next, in order to prevent aliasing distortion due to thinning, a low-pass filter 101 attenuates frequency components of (3,375/2) M7 or higher, and a thinning circuit 102 performs thinning, so that the number of pixels in the horizontal direction is reduced from the original. is half the number of pixels. Next, the block generator 103 divides the blocks into blocks of (8 pixels x 8 lines), but as mentioned above, the number of horizontal pixels after thinning is 180, which is not an integral multiple of 8. A23 in FIG. 2(a). B2
As shown in FIG. 3, only the 23rd blocks in the horizontal direction are small blocks of different sizes (4 pixels x 8 lines). Therefore, as shown in FIG. 2(b), the adjacent A
23 and B23 are combined into one block (8 pixels x 8 lines). In this case, the number of vertical blocks is 2
Since it is a multiple of , it can be divided into a total of (45x15) blocks.

The block generator 103 performs the blocking described above.
It has three memories for 8 lines, one of the three memories is used for writing, and the remaining two are used for reading, and by switching between writing and reading in units of 8 lines, The above-mentioned blocking can be realized. That is, memories 105 and 106 are used for reading, and memory 1 is used for reading.
When using 07 for writing, as shown in FIG. 3(a), 8 lines of data are sequentially written into the memory 107, and at the same time, as shown in FIG. .106 is read out alternately. In this case, switch 104 is used for writing memory 1
07 is selected, and the switch 108 alternately selects the memory 105 and the memory 106 for reading in block units.

Here, as shown in FIG. 2(b), when adjacent small blocks are combined into one block, if there is no correlation between the two small blocks, the high-frequency components are converted by the DCT operator 109. occurs, reducing compression efficiency, but no significant deterioration in image quality occurs.

Furthermore, in general image signals, there is a high probability that the correlation between adjacent small blocks is strong, so this does not pose a particular problem.

As explained above, according to this embodiment, adjacent (4
By combining blocks of (pixels x 8 lines) into one block of (8 pixels x 8 lines), the entire screen is
It is possible to divide the image into blocks of 8 pixels x 8 lines) and is easy to implement.

In addition, in this example, the case where the current system component signal is divided into blocks in units of (8 pixels x 8 lines) was taken up, but the number of pixels and the size of the blocks are as explained in this example. It can be applied to things that have a similar relationship to things.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, when dividing an image signal into blocks, even when the number of horizontal pixels is not equal to an integral multiple of the number of horizontal pixels of one block, block division can be easily realized. It can be done and its effectiveness is high.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a signal processing device according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing a method of dividing into blocks, and FIG. 3 is a block diagram of a signal processing device according to an embodiment of the present invention. Fig. 4 is a block diagram of a conventional signal processing device, and Fig. 5 shows a method of writing to and reading from memory in a conventional signal processing device. It is an explanatory diagram. 3.103...Blocker, 4. 7.10
4.108...Switch, 5. 6.105.
106.107...8 line memory. Name of agent Patent attorney Shigetaka Awano 1 person 12 Figure (a) Cancer r line 1--□------1--1 45 Frowak

Claims (2)

[Claims] (1) When dividing an image signal having (m×i+j) horizontal pixels into blocks (m>j), divide the image signal into a block consisting of m pixels in the horizontal direction and n lines in the vertical direction and j pixels in the horizontal direction and vertically. A signal processing device comprising: means for dividing into small blocks each having n lines in a direction; and means for collecting a plurality of said small blocks to form said block. (2) The signal processing device according to claim (1), wherein the block is configured by collecting a plurality of adjacent small blocks.