JPH0456572A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To display a slave pattern at part of a master pattern by providing a timing control circuit deciding a drive timing for a drive circuit for a solid- state image pickup element based on a horizontal synchronizing signal and a vertical synchronizing signal of a video signal to the device. CONSTITUTION:A synchronizing separator circuit 10 separates a synchronizing signal CS from a video signal X0t and gives it to a horizontal and vertical signal separator circuit 11 and gives a video signal X1t to a signal synthesis circuit 12. Moreover, a timing generating circuit 16 is operated according to a horizontal synchronizing signal HS1 and a vertical synchronizing signal VS to generative timings DTH, DTV for horizontal and vertical scanning synchronously with the synchronizing signals HS1,VS. In this case, a solid-state image pickup element 15 to obtain a 2nd video signal is driven synchronously with a lst video signal to obtain the 2nd video signal synchronously with the lst video signal in advance and part of the lst video signal is replaced into the 2nd video signal to synthesize the lst and 2nd video signals without storing the 2nd video signal once to the memory. Thus, the synchronization display of the master pattern and the slave pattern is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a solid-state imaging device that displays a sub-screen on a part of a main screen by superimposing a sub-screen video signal on a main screen video signal. .

(b) Prior Art FIG. 5 is a block diagram of a video signal processing circuit that superimposes a video signal of a child screen on a video signal of a main screen.

The television camera (1) that obtains the video signal x(t) of the main screen operates according to the synchronization signal C8, which is created within the camera, and outputs this synchronization signal C5l together with the video signal X,t. Generally, the video signal component is superimposed on the synchronization signal C8° and output, and the synchronization signal component and the video signal component are separated on the receiving side. In addition, the video signal Y (
Similarly, the television camera (2) that obtains the video signal Y(t) operates according to the synchronization signal CSz created within the camera, and outputs the synchronization signal C8, together with the video signal Y(t).

A TV camera that operates with its own timing in this way (
1) Video signal obtained from (2) X, t, , Y, t
.

, the horizontal and vertical scan timings are not consistent,
Since it is not possible to overlap them directly, the video signal Y (t) of the sub-screen is stored in the field memory for -10 minutes.
The video signals X(t) and Y(t) are synchronized by reading them from the field memory at a timing according to the synchronization signal C81 of the parent screen.

For example, the video signal Y(t) is converted into digital data by the A/D conversion circuit (3), inputted to the screen control circuit (4), and stored in the memory (5) according to the synchronization signal C82. Then, it is detected from the memory (5) at the timing according to the synchronization signal C81, and from the screen control circuit (4) the D/A
It is output as a video signal Ml(t,) via a conversion circuit (6). This video signal Yl(t) is the video signal xct
) constitutes a child screen that is smaller than the main screen indicated by the screen, and the video signal components in the horizontal and vertical directions are created by thinning out or combining the data of the video signal Yct from the television camera (2) into an appropriate number of bits. is reduced. The video signal Yl(t) reduced in this way can be output according to the synchronization signal C5, and is outputted according to the selection pulse ST synchronized with the effective video period of this video signal Y,,t. ) can be replaced with That is, the selection pulse ST
The signal synthesis circuit 7, which is switched and controlled according to the selection pulse S, selects the video signal x(t) from the television camera (1) and the video signal Y'+(t) from the screen control circuit (2).
The video signal Y is configured to select and output according to T, and the video signal Y
The video signal Y, (t) can be selected only during the effective video period of I(t). Therefore, the video signal Y, (t) is displayed in a part of the main screen.
A video signal Z (t) is obtained that allows the sub-screen to be completely displayed.

The position where the child screen is displayed is determined by the timing of outputting the image signals Y, t), and the position where the child screen is displayed is determined by the timing of outputting the image signals Y, , t).
The display position is set by setting the output delay of l(t). For example, if the output of the video signal YI(1) is delayed with respect to the horizontal scanning timing of the synchronization signal C8, the display position will move closer to the right side of the screen, and if it is delayed with respect to the vertical scanning timing, the display position will be closer to the bottom of the screen. comes closer to.

According to the signal processing circuit as described above, a reduced child screen can be displayed on a portion of the screen where the main screen is displayed, and two screens can be displayed simultaneously on one monitor.

(c) Problems to be Solved by the Invention However, in the signal processing circuit as described above, it is necessary to store part of the video signal in the field memory, so the memory (5), A/D converter (3) ), a D/A conversion circuit (4), etc., resulting in a large circuit scale.

In particular, an A/D conversion circuit (3) for processing video signals.
Since the D/A conversion circuit (4) is required to operate at high speed, it has a special configuration, which is a factor that increases costs.

Furthermore, since the circuit scale becomes large, it is difficult to incorporate it into a television camera, and a device for processing the video signal is required. Therefore, it is not possible to construct an inexpensive imaging system.

(d) Means for Solving the Problems The present invention has been made to solve the above-mentioned problems, and is characterized by the fact that the first
A third video signal for displaying the second screen on a part of the first screen is generated by combining the video signal with a second video signal constituting a second screen smaller than the first screen. The solid-state imaging device to be obtained includes a solid-state imaging device in which a plurality of light-receiving elements are arranged in a matrix and generates information charges according to a received image pattern, and the above-mentioned second method is achieved by transferring and outputting the information charges of this solid-state imaging device. A drive circuit that obtains a video signal, a detection circuit that detects horizontal and vertical synchronization signals of the first video signal, and a timing control circuit that determines drive timing of the drive circuit based on the synchronization signal from the detection circuit. and a signal synthesis circuit that selects and synthesizes the first or second video signal in synchronization with the operation of the drive circuit.

(f) Function According to the present invention, by driving the solid-state image sensor that obtains the second video signal in synchronization with the first video signal, the second video signal synchronized in advance with the first video signal is generated. By replacing a part of the first video signal with the second video signal, the first video signal can be transferred to the first video signal without storing part of the second video signal in the memory.
and a second video signal can be synthesized.

Kuhe) Examples An embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the solid-state imaging device of the present invention.

The video signal xo(f-) constituting the main screen is obtained from a television camera (not shown) that operates at its own timing, and includes a video signal component and a synchronization signal component. The synchronization signal separation circuit 10) receives the video signal X5(t)
The synchronizing signal C8 is separated from the synchronizing signal C8 and further supplied to the horizontal/vertical separating circuit (11), and the video signal XI(t) is supplied to the signal combining circuit (12). Horizontal/vertical separation circuit (1
1) separates the synchronization signal C8 supplied from the synchronization signal separation circuit (10) into a horizontal synchronization signal H8 and a vertical synchronization signal ■S. The horizontal synchronizing signal HS e is input to the phase comparison circuit (14) together with the horizontal synchronizing signal H5 from the horizontal synchronizing signal generating circuit (13) having its own oscillation source, and the horizontal synchronizing signal is generated according to the comparison output FD. Circuit (1
3) oscillation source, for example, V CO (Voltage Co
The horizontal synchronizing signal H8 is synchronized with the horizontal synchronizing signal H5 supplied from the outside by controlling the oscillation frequency of the horizontal synchronizing signal H5.

On the other hand, the solid-state image sensor (15) that obtains the video signals Y,,t, constituting the child screen is a CCD that operates according to the drive timing DT supplied from the timing generation circuit (16).
The video signal yo is pulse-driven by the drive clock DS from the driver (17) and synchronized with the drive timing DT.
ct> is supplied to the video signal processing circuit (18). The video signal processing circuit (18) performs processing such as sample hold and gamma correction on the video signal Y0(1), and supplies the video signal Y, t) to the signal synthesis circuit (12).

The timing generation circuit (16) operates according to the horizontal synchronization signal H8I and the vertical synchronization signal VS, and generates each synchronization signal H3,
, horizontal and vertical scanning drive timing D synchronized with VS
Generates TH and DTv. That is, the timing generation circuit (
16) sets the display position of the sub-screen by delaying the horizontal synchronizing signal H5l and the vertical synchronizing signal S by an appropriate period, and is composed of, for example, a counter and a decoder as shown in FIG.

The horizontal carantuff 20) is reset by the horizontal synchronizing signal H5l and counts with the basic clock CK from the oscillation source of the horizontal synchronizing signal generating circuit (13), and inputs its output to the decoder (21).The decoder (21) , the horizontal scanning drive timing DT is generated by decoding the output of the horizontal counter (20).Therefore, the drive timing DTH is based on the basic tally C with respect to the horizontal synchronizing signal H8°.
The output timing of the video signal Y, t) is delayed by an integral multiple of K, and the output timing of the video signal Y, t) is the horizontal synchronization signal HS+, that is, the video signal X, t)
The horizontal scanning output timing is set to be delayed by a predetermined period with respect to the horizontal scanning output timing.

Further, the vertical counter (22) is reset by the vertical synchronizing signal vS, counted by the horizontal synchronizing signal H8, and inputs its output to the decoder (23). Therefore, the decoder (
23) generates a vertical scanning drive timing DTv delayed by an integral multiple of the horizontal scanning period with respect to the vertical synchronizing signal vS by decoding the output of the carantuff 22),
The output timing of the video signal Y,t is the video signal XICt
) is set to be delayed by a predetermined period with respect to the output timing of vertical scanning.

On the other hand, horizontal and vertical scanning drive timings DT, DT
The selection pulse generation circuits (24) and (25) which receive the selection pulses ST, STv and generate the selection pulses ST, STv, generate the video signal Yi(t).
The signal synthesis circuit (12) is controlled to select and output Yl(t) in synchronization with the output timing of . That is, the selection pulse generation circuits (24) and (25) drive the signal synthesis circuit (12), which constantly selects the main screen video signal , t) side, and after a predetermined period, switches again to the video signal t) is obtained.

By the way, as shown in Figure 3, the child screen is 1/1 of the main screen.
For the size of n, the video signal Y, (t) is the video signal X
(Since the amount of information is 1/n of t, the amount of information is 1/n of the main screen.
The video signal Yl(t) for the child screen is obtained by providing a CCD with the number of pixels corresponding to n, or by thinning out the signal at appropriate intervals in the signal processing stage. Therefore, the video signal Y,, t) is 1 as shown in FIGS.
A video signal X having video information in a horizontal scanning period (IH) and one vertical scanning period (1v).

In contrast to (1), video information is provided in periods H/n and V/n. Therefore, the selection pulses ST and STv are set in synchronization with the valid period of the video signal YI(t). The display position of the child screen is at the rising timing of the video signal Y1, CE, that is, at the drive timing DT.

This is determined by the period in which the DT master lags behind the horizontal synchronizing signal H3 and vertical synchronizing signal Vs, and is
) (23) can be variably set by setting the decode value. For example, when the counters (20) and (22) count up, the larger the decoded value of the decoder (21>), the more the sub-screen is displayed on the right, and the more the decoder (23)
The larger the decode value, the lower the sub screen will be displayed.

In this embodiment, counters are used to obtain drive timings DTa and DTv, but shift registers and various delay circuits are also used to obtain horizontal synchronization signals H8 and vertical synchronization signals. The drive timings DT H and DT v can also be obtained by delaying the signal vS.

(G) Effects of the Invention According to the present invention, since the video signal of the child screen synchronized with the video signal of the main screen can be obtained in advance, there is no need to synchronize the video signal at the signal processing stage, and the video signal is temporarily stored. The additional circuit can be omitted. Therefore, the main screen and the child screen can be displayed simultaneously with an extremely simple circuit configuration.

Furthermore, by providing the solid-state imaging device itself with a video signal superimposition function, processing of video signals obtained from the device becomes easier, and video from a surveillance camera such as a doorbell can be displayed on a general television screen. Therefore, an inexpensive and simple monitoring system can be constructed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the solid-state imaging device of the present invention, Figure 2 is a block diagram of the timing generation circuit, Figure 3 is a schematic diagram of screen display, Figure 4 is an operation timing diagram, and Figure 5 is video signal processing. FIG. 2 is a block diagram of the device. (1) (2)...Television camera, (4)...Screen control circuit, (5)...Memory, (7) (12)
...Signal synthesis circuit, (10) ...Synchronization signal separation circuit, (11) ...Horizontal/vertical separation circuit, (13).
...Horizontal synchronization signal generation circuit, (14) ...Phase comparison circuit, (15) ...CCD solid-state image sensor, (16)
...timing generation circuit, (17) ...CCD driver, 18) ...video signal processing circuit, (20
) (22)...Counter, (21)(23)...
・Decoder, selection pulse generation circuit. (24) (25)...

Claims (2)

[Claims] (1) A first video signal that makes up a first screen is combined with a second video signal that makes up a second screen that is smaller than the first screen, and the second video signal is added to a part of the first screen. A solid-state imaging device that obtains a third video signal for displaying a screen includes: a solid-state imaging device in which a plurality of light-receiving elements are arranged in rows and columns and generates information charges according to the image pattern received; and information on this solid-state imaging device. a drive circuit that obtains the second video signal by transferring and outputting a charge; a detection circuit that detects horizontal and vertical synchronization signals of the first video signal; and a drive circuit that detects the horizontal and vertical synchronization signals of the first video signal, and drives the drive circuit based on the synchronization signals from the detection circuit. A solid-state device comprising: a timing control circuit that determines the drive timing of the circuit; and a signal synthesis circuit that selects and synthesizes the first or second video signal in synchronization with the operation of the drive circuit. Imaging device. (2) The first video signal includes horizontal and vertical synchronizing signal components, and the synchronizing signal component is separated from the first video signal to set the operation timing of the drive circuit. The solid-state imaging device according to item 1.