JPH0456578A - Video signal processing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a video tape recorder (hereinafter abbreviated as VTR).
The present invention relates to video-signal processing devices such as the following.

BACKGROUND OF THE INVENTION In recent years, as VTRs have become more sophisticated and have higher image quality, various special playback techniques have come into use. A conventional video signal processing device will be described below.

FIG. 5 shows an example of a pseudo vertical synchronization signal generation circuit in a conventional video signal processing device. FIG. 6 shows pulse waveforms in the pseudo vertical synchronization signal generation circuit. In order to detect the first equalization pulse 42 from the reproduction separation synchronization signal 40, 3μsee is applied based on the falling edge of the reproduction separation synchronization signal 40.
The width pulse generator 30 generates a 3 μsec wide pulse 41.
◇At the riser of the 3μsec width Norx 41, the synchronization pulse of the regeneration separation synchronization signal 40 is sampled to form an equivalent pulse (2.3μ5ec) narrower than the horizontal synchronization pulse (4.7μ5ec). Perform detection. The first equalization pulse detection circuit 31 detects the first equalization pulse 42, and the 1/2H pulse generation circuit 32 shapes the 1/2H width pulse 43 using the first equalization pulse.
The second equalization pulse 44 that follows 2H is detected by the second equalization pulse detection circuit 33. Note that H represents the period of the horizontal synchronization signal. The second equalization pulse is shaped into a timing pulse 45 by the timing pulse generation circuit 34,
A timing period t is taken that is equivalent to the phase of the reproduction separation synchronization signal 40, and the pseudo vertical synchronization signal generation circuit 35 generates a pseudo vertical synchronization signal 46. The cycle is ensured.

However, with the above configuration, when the period of one field changes, it is not possible to detect whether the mode is normal playback mode or variable speed playback mode. In addition, in the case of CUE (playback fast forward)/REV (playback rewind) in variable speed playback, if the playback synchronization signal expands or contracts, the only way to pull it in is with APC, etc. that controls the phase of the synchronization signal, so the standard vertical synchronization signal is not output. As a result, there is no vertical period of the synchronization signal that changes in a pseudo manner, causing a phenomenon in which the screen moves.

Means for Solving the Problems Among the above problems, the video signal processing device of the present invention uses a mode detection counter to distinguish between normal playback mode and variable speed playback mode, in order to detect differences in modes during playback. . In addition, in order to exchange the vertical synchronization signal at the time of CUE/REV, a vertical synchronization separation circuit that separates the vertical synchronization signal from the reproduced video signal, a falling edge and rising edge detection circuit, a mode detection counter, Vertical synchronization period detection counter, data type flip-flop, +3H
It consists of a shift circuit, an expansion/contraction value adjustment decoder, and a crystal oscillation circuit.

According to the above-described structure, the present invention detects the shift amount of the reproduction vertical synchronization signal including the mode detection method using the mode detection counter, thereby changing the period of one fixed field period during variable speed reproduction. It is possible to control the replacement of the shift vertical synchronization signal without having to do so.

Example .

FIG. 1 is a block diagram showing an embodiment of a video signal processing device of the present invention. Fig. 2 is a waveform diagram showing the operation in Fig. 1, Fig. 3 is a waveform diagram showing the operation of the vertical synchronization signal at CUE/REV, and Fig. 4 is a waveform diagram showing the delay amount of the vertical synchronization signal. FIG. This will be explained below with reference to the drawings. In FIG. 1, 1 is a vertical synchronization separation circuit, 2 is a crystal oscillation circuit, 3 is a falling edge detection circuit, 4 is a rising edge detection circuit, 5 is a mode detection counter, and 6 is a vertical synchronization period shift detection counter, 7 is a data type flip-flop,
8 is a +3H shift circuit, and 9 is an expansion/contraction value adjustment decoder.

The operation of the video signal processing configured as above will be explained below. The reproduced video signal 10 is input to a vertical synchronization separation circuit 1, which outputs a reproduced vertical synchronization signal 11. At this time, since a delay amount l occurs between the reproduced video signal 10 and the reproduced vertical synchronizing signal 11 as shown in FIG. 4, the fall of the reproduced vertical synchronizing signal 11 is used as the reference for signal processing.

The reproduced vertical synchronization signal 11 is input to a falling edge detection circuit 3, a rising edge detection circuit 4, and a vertical synchronization period shift detection counter 6. As shown in FIG. 2, the falling edge detection circuit 3 outputs a falling edge pulse 13 at the falling edge of the reproduced vertical synchronization signal 11, and inputs this signal to the data type flip-flop 7. Further, the rising edge detection circuit 4 outputs a rising edge pulse 14 at the rising edge of the reproduced vertical synchronizing signal 11, and inputs the signal to the mode detection counter 5. Here, since the period of one field is fixed to 525/2r+, one field period is counted as 262.5u. Therefore, as shown in FIG. 4, from the crystal oscillation circuit 2,
A 2fH clock signal 12 is output, and the signal is sent to the mode detection counter 5 and the vertical synchronization period detection counter 6.
is input. Note that fH indicates the horizontal synchronization frequency. The mode detection counter 5 uses the rising edge pulse 14 as a clear pulse, and at the same time as the rising edge pulse 14 is input, it counts up to the next rising edge pulse at a clock cycle of 2fH.

At this time, the reproduction vertical synchronization signal 11 at CU E/RE V
As shown in FIG. 3, the playback fast-forward vertical synchronization signal A is compressed during CUE, etc., and the playback and rewind vertical synchronization signal B is extended during REV, causing expansion and contraction. For example, the shift amount during CUE can be determined from the following equation.

(For CUE) 262.5+(1-α)・αH・・・・■α: Double speed number αH: Number of modes...2 hours 1.56 hours 0
．． 5. Calculating 90x speed and 30x speed in 2-hour mode and 6-hour mode from formula 5.90x 30x speed 2 hours 129H219H 6 hours 218H248H. The shift amount j is maximum at 262,5(H)-129(H)-133,5(H) when the speed is 90x in the 2-hour mode, and 262,5(H) when the speed is 30x in the 6-hour mode.
The minimum value is H)-248(H)=14.5()I).

It can be seen that there is a shift amount greater than that. In addition, at the time of REV, it can be obtained from the following equation.

262.5+(1+α)・αH・・・・・・■For this reason, the mode detection counter 5 counts at 2fH, so the count of one field is maximum 792, and the output signal 15 of the mode detection counter 5 is The data is input to the data type flip-flop 7 as 10-bit binary data.

Depending on the amount of data at this time, it can be determined whether the mode is normal playback mode or variable speed playback mode. The data type flip-flop 7 inputs data to the +3H shift circuit 8 when the falling edge pulse 13 is input. Since 10-bit binary data is input to the data type flip-flop 7, 10 stages of data type flip-flops 7 are required.

On the other hand, the vertical synchronization period shift detection counter 6 detects the cycle of the input reproduced vertical synchronization signal 11, and uses this value as the shift amount of the vertical synchronization signal. From Figure 2, this means that in the current field, the period of one field is counted at 2fH, and when CUE/REV starts from the next field, the count amount for one field is reflected.
It is output to the expansion/contraction value adjustment decoder 9. Data 18 from the +3H shift circuit 8 is also input to the expansion/contraction value adjustment decoder 9 . The +3H shift is performed because the vertical synchronization period shift detection counter 6 detects the cycle of one field, and from C in FIG. 4, the equivalent pulse m of 3H is in the synchronization period. It is necessary to shift by 3H to match the falling edge of the vertical synchronization signal. Therefore, data shifted by 3H to the data 16 output from the data type flip-flop circuit 7 is input to the expansion/contraction value adjustment decoder 9. The expansion/contraction value adjustment decoder 9 constantly receives data for one field period from the vertical synchronization period shift detection counter 6, and also calculates the shift amount of the vertical synchronization signal from the expansion/contraction value +3H data from the +3H shift circuit 8. and outputs the pseudo vertical synchronization signal 19.

Effects of the Invention As described above, the present invention detects the mode difference between the normal playback mode and the variable speed playback mode, and
At the time of E/REV, the vertical synchronization signal can be changed dramatically without changing the period of the l 7 yield.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a video signal processing device in an embodiment of the present invention, Fig. 2 is a waveform diagram showing the operation in Fig. 1, and Fig. 3 shows the operation of the vertical synchronization signal during CUE/REV. 4 is a diagram showing the delay amount of the vertical sync signal, FIG. 5 is a block diagram showing an example of a conventional pseudo vertical sync signal generation circuit, and FIG. 6 is a diagram showing the delay amount of the vertical sync signal. FIG. 3 is a waveform diagram showing a pulse waveform. 1... Vertical synchronization separation circuit, 2... Crystal oscillation circuit, 3... Falling edge detection circuit, 4...
... Rising edge detection circuit, 5 ... Mode detection counter, 6 ... Vertical synchronization period shift detection counter, 7 ... Data type flip-flop, 8 ...+3H shift circuit, 9...
・Stretching value adjustment decoder, 10... Reproduction video signal, 11... Reproduction vertical synchronization signal, 12...
・2f+clock signal, 13... Falling edge pulse, 14... Rising edge pulse, 15...
...10-bit binary data, 16...
...1 field vertical synchronization shift amount data, 17...
...1 field detection data, 18...1 field vertical synchronization period shift amount + 3H data, 19...
...Pseudo vertical synchronization signal, 30...3μse
c-width pulse generator, 31...first equalization pulse detection circuit, 32...1/2H pulse generation circuit, 3
3...Second equalization pulse detection circuit, 34...
... Timing pulse generation circuit, 35 ... Pseudo vertical synchronization signal generation circuit, 40 ... Reproduction separation synchronization signal, 41 ... 3 μSeC width pulse, 42 ...
...First equalization pulse, 43...1/2Hm
Pulse, 44... Second equalization pulse, 45...
... Timing pulse, 46 ... Pseudo vertical synchronization signal, A ... Vertical synchronization signal during playback fast forward (C
UE), B...Vertical synchronization signal during playback and rewinding (
REV time), C...Playback video signal synchronization period, D
...Vertical synchronization signal, E...Nft V,
A, timing, h... 1 field period, i
...Decoded value +3H, j...Reduced value, k...Expanded value,! ...Delay amount, m
...Equivalent pulse (3H), t...Timing period. Name of agent: Patent attorney Shigetaka Awano

Claims (1)

[Claims] (1) A vertical synchronization separation circuit that separates a vertical synchronization signal from a reproduced video signal, a falling edge detection circuit that detects a falling edge of the vertical synchronization signal, and a rising edge detection circuit that detects a rising edge of the vertical synchronization signal. a crystal oscillation circuit that oscillates at twice the horizontal synchronization frequency, a mode detection counter that receives the output signals of the rising edge detection circuit and the crystal oscillation circuit and detects a mode, and the vertical synchronization separation circuit. A data type into which the output signal of the crystal oscillator circuit is input, a vertical synchronization signal shift detection counter for shifting the vertical synchronization signal period, and the output signals of the falling edge detection circuit and the mode detection counter are input. A +3 horizontal period shift circuit that receives the output signal of the flip-flop of the same data type as the flip-flop and shifts it by +3 horizontal periods, and an expansion/contraction value that receives the output signals of the +3 horizontal period shift circuit and the vertical synchronization period shift detection counter. It has an adjustment decoder and uses the difference between the vertical synchronization signal in normal playback mode and the vertical synchronization signal in variable speed playback mode to detect the difference in mode and replace the vertical synchronization signal during variable speed playback. A video signal processing device characterized by: