JPH04569A - Layout editor device with automatic resistance generating function - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a layout editor device that automatically layouts a resistance pattern in a semiconductor device.

[Conventional technology]

Conventionally, when inputting a pattern in a semiconductor device, information must be specified for each bending point. FIGS. 4 and 5 are plan views showing examples of conventional pattern data input.

Next, a pattern input operation will be explained.

There are two methods for input operations:

(7) Input by specifying the outline As shown in FIG. 4, the pattern is assumed to be a polygon, and input is made by specifying the coordinates of all its vertices F, G, H, I, J, and K.

(b) Input by specifying the center line and width As shown in Figure 5, consider the pattern as a polygonal line, and input by specifying both 12tllP and M of the center line, the bending point Q, and the pattern width ω. .

[Problem that the invention seeks to solve]

Conventional layout editor devices create patterns using more than one method, so in order to input a long resistance in a limited space, a lot of information must be specified in the nibbutting operation, which requires manual labor. There were problems such as increased number of interventions, input errors, and increased pattern design time.

This invention was made to solve the problems mentioned above, and it reduces pattern input errors, and
The object of the present invention is to obtain a layout editor device with an automatic resistance generation function that can shorten the pattern design period.

"Means for Solving the Problems" The V-wire editor device with automatic resistance generation function according to the present invention automatically generates resistance with a specified resistance value between two specified points while observing the design rules. It has a function.

[Function] In this invention, Z, a layout editor device with an automatic resistance generation function, selects a resistor that satisfies the specified NFC and resistance value,
It is generated by applying the maze method while checking against the file that describes the design rules.

The difference from the normal maze method is that instead of searching for the shortest route, it searches for a route that titrates a specified resistance value.

However, since the resistance value is related to the width and length, first
Divide it into grids with slightly larger side lengths, apply the maze method there, select a slightly longer route with the least number of bends, and finally modify @ downward to satisfy the resistance value.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
The colors are a plan view showing an example of resistance pattern input to a layout editor device with automatic resistance generation function, Figure 2 is a flowchart of resistance pattern input, and Figure 3 is a plan view showing an example of resistance pattern route search. In figure 0, (1)
is the resistance pattern s to be generated (2)b: another pattern on the same layer, (3) is the resistance generation limit according to the design rule, 01) is the step to be generated, (4) is the resistance pattern to be generated The starting point of the resistance pattern fil to be generated, the end point of the resistance pattern to be generated in (B), Ic) tr
i is the prohibited area, 0 is the shortest route, and (6) is the adopted route.

When the user specifies the start point, end point (B), resistance value, and layer, the occurrence limit (3) will be set from the design rule file for the same layer as the specified pattern and for the file that stores the position of the collar turn (2). Resistance pattern (1) with a specified constant resistance at- determined and within that range
is generated.

The method of generating a resistance pattern (1) t- having a specified constant resistance value within an allowable space is to control L and this in a program.

If it is impossible for this to occur, a message to that effect is output to the program.

Next, the flowchart shown in FIG. 2 will be explained using FIG. 3.

In addition, the following (6)-mother is the step 0υ~■ in Figure 2.
This is an explanation.

0η Compare the width W of the narrowest part of the input limit region with the process-specific minimum resistance width a4 '1 defined in the design rules +
W(" If it is o, it is impossible to generate the resistance pattern (11), so an error message to that effect is output and the program is terminated.

If @W≧proboscis, it will take some time to prepare for the generation of the resistance pattern fl), but from the beginning the resistance pattern it with the width of the proboscis
), it will cause problems during later corrections, so
Margin coefficient k (k>1)′f! : The multiplied value ω is the resistance width.

(To) Resistance width ω, specified resistance value R, and sheet resistance value P8 specified in the design rules Rainbow resistance pattern (1)
length! Calculate.

Compare the shortest distance LTh between α←R start point and end point FB),!
<If it is L, it is impossible to generate resistance pattern (1), so an error message to that effect is output and the program is terminated.

However, the shortest distance refers to the length of the shortest route when the resistance pattern (1) occurs in the horizontal and vertical directions in the region where it can occur. (In the example in Figure 3, the shortest route is the shortest route (D) and its length is L = 16ω, so an error occurs when !<16ω.) (G)! If ≧, the route search stage for generating the resistance pattern fi1 is entered. Grid division is performed using ω as the side length.

As shown in Figure 3, the maze method is numbered from both the starting point and the ending point. aid is the maze number from the starting point (A), b is the maze number from the end point (B). α7) a + b −! -n2'Yc? R plus tangent 1
exists (-(b field 8 - si J case (in the example of Fig. 3, when ρ>40) 5 resistance...: turn i1). Outputs the message and ends the program.

Here, −, p is the resistance and the (1) Ω bending circuit, and 2
, the compensating pressure deficiency of the resistance value in the bending of the resistance pattern fl) is ζ
If there are two points, 8 - υ is the most f among them, I teka, :) a '-b
Take the route that minimizes a rx, i.e., Figure 3) Since g is 20, a=
l I, b = 1 + +7) ,':$
ThB + B-to = 26-i, which is the minimum value of 9 or more, so the resistance...<me), select the adopted route section for -fl+ 0 (19a + b - "n =" 5. h 5, adjust ω downward 11 (iJ Especially, work 9. Resistance ia R': '-''Resistance' + main (1) is generated at til after Oj correction that eliminates the gap difference.' In the above embodiment, the case where the resistance pattern fl+ is generated (':) is shown, but when generating a pattern such as wiring, etc., when it is desired to generate 5 or more butters 7 on the same length, the same method as in the above embodiment may be used. 5. In this case, specifying the length rather than the resistance value is effective.
i) ゛Since it is fixed for each seven degrees, it is possible to search and generate 7゜ in a unique manner5.

[Effect of the invention 1 If the above = 5, this invention (・te, n, then the resistance bench l −
If you specify the start and end point resistance values of the turn, the resistance/turn will be automatically generated, reducing the number of turns.

This has the effect of shortening the pattern design period.

[Brief explanation of the drawing]

iJ diagram is here. FIG. 3 is a plan view showing an example of searching for a resistance butter flute, and FIG. 5 is a plan view showing an example of a conventional butter flute search by hand. , In the figure, 1ll('i resistance pattern, (2 penalty ↓ other patterns on the same layer, (3) is the generation limit, qη ~ (5) is the sushi soge, (A) I-j starting point, cBHt ending point, (0 is the prohibited area, (D) is the shortest route, and the figure is the adopted route. In the figure, the same reference numerals are the same and indicate the portion corresponding to ζ・1.

Claims (1)

[Claims] By specifying the starting point, ending point, and resistance value of the resistance pattern when generating the resistance pattern of the semiconductor device,
Read the process-specific minimum resistance width and sheet resistance value from the file that describes the design rules, calculate the resistance width from these, divide it into grids with side lengths larger than the resistance width, and apply the maze method to minimize the number of bends. A layout editor device with an automatic resistance generation function, characterized in that a desired resistance pattern is obtained by selecting a route with the closest length and finally correcting the resistance width to eliminate errors in resistance values.