JPH0457021B2 - - Google Patents

Description

[Detailed description of the invention]

[Overview] A microprogram type information processing device that has a register for storing machine language instructions consisting of a plurality of registers for different uses, and stores each part of the fetched machine language instructions in the registers for different uses for processing. Conventionally, when fetching a machine language instruction, the operation code is decoded to determine in which register the fetch data should be stored. When the fetish timing comes,
There is a problem in that time is wasted between the fetch timing and the next fetch timing. In order to solve the above-mentioned problems, the present invention has been made such that when fetching a machine language instruction, the fetch timing is determined before a determination result is obtained as to which register among the plurality of application-specific registers the fetch data should be stored in. By simultaneously storing the fetch data in multiple registers that may store the fetch data among multiple application-specific registers, no wasted time is generated, thereby increasing processing speed. A control method that can be used is disclosed. [Industrial Field of Application] The present invention relates to the control of preprocessing related to the execution of machine language instructions in a microprogram type information processing device, and in particular, the present invention relates to the control of preprocessing related to the execution of machine language instructions in a microprogram type information processing device. This relates to control when storing data in registers. [Prior Art] Information on a microprogram system that has a register for storing machine language instructions consisting of a plurality of registers for each purpose, and stores each part of the fetched machine language instruction in each of the registers for each purpose for processing. Conventionally, when a processing device executes a machine language instruction, it first fetches and decodes the opcode of the machine language instruction, and then, depending on the result, performs predetermined fetches on other parts following the opcode. stored in a register. To further explain the operation of the microinstruction at this time, the microinstruction fetches the opcode of the machine language instruction, stores the opcode in a fetch register for decoding the opcode, and decodes it. Then, in accordance with the result, the part after the opcode (part of the operand) of the machine language instruction is fetched and stored in a fetch register having the corresponding purpose. These operations are repeated until all parts of one machine language instruction have been fetched. During this time, processing (for example, address calculation) may be performed on a portion that has already been fetched. Figure 2 shows an example of the format of machine language instructions, (a)
shows the format of instruction A, and (b) shows the format of instruction B, where 1 represents the opcode, 2 represents the first operand, and 3 represents the second operand. Then, the opcode of instruction A is OP-A, and the opcode of instruction B is OP
-B, and the first operand is instruction A.
is R ₁ , instruction B is B×D, and the second operand indicates that instruction A is R ₂ and instruction B is R ₁ . FIG. 3 is a diagram showing an example of instruction fetch registers, in which 4 to 7 are fetch registers, 4 is FR0, 5 is FR1, 6 is FR2, and 7 is FR.
It represents 3. Each fetch register has a function or use shown in Table 1. When processing instruction A or instruction B using an instruction fetch register as shown in Figure 3,

[Problem that the invention seeks to solve]

As mentioned above, in the conventional method, in order to fetch the first operand of a machine language instruction into a predetermined register, the operation code must have been decoded by then, and the microprocessor must determine which fetch register to store it in. It is necessary to instruct by command. FIG. 4 is a time chart showing conventional control related to fetching of machine language instructions, in which a indicates the case of instruction A, b indicates the case of instruction B, 8 indicates the fetch timing, and 9 indicates the fetch timing. Action, 10-1
3 is each fetish register (FR0~FR
3) represents the timing at which data is stored, and 14 represents the operation of the microinstruction. In FIG. 4a, the operation code OP-A is fetched at timing and stored in FR0 by a microinstruction, decoded at timing, the result is checked, and the data fetched from the first operand at timing (R ₁ ) is stored in FR3. Furthermore, at timing, the second operand data (R ₂ ) is fetched and stored in FR2. In the case of instruction B shown in FIG. 4b, the contents of the operands are different from those of instruction A, so the fetch register that stores them is different, but the timing conditions are different from those in the case of FIG. 4a. It's exactly the same. As is clear from Figures 4a and b,
In timing, the microinstruction decodes the opcode fetched at the timing, and the result is obtained, and the contents of the operand are known and can be stored in the corresponding fetch register. Since this occurs after the timing, the fetch operation cannot be performed at the timing. From the perspective of efficiently and quickly fetching each part of a machine language instruction, this causes a large time loss, and is one of the factors that reduces the processing speed related to machine language instruction execution. It is what it is. The present invention solves these conventional problems and
It is an object of the present invention to provide a control method that does not cause time loss when fetching the operand part of a machine language instruction. [Means for Solving the Problems] According to the present invention, the above object is achieved by combining an opcode part and at least one
In a microprogram type information processing device that sequentially fetches each part of a machine language instruction consisting of two operand parts and stores each part in a register for each purpose for processing, when fetching a machine language instruction, the first operand is fetched. When the timing comes, before the result of decoding the operation code that determines which of the application-specific registers the fetch data should be stored in is obtained, the fetch data in the application-specific register is stored in the corresponding instruction. This is achieved by a machine language instruction preprocessing method that controls the simultaneous storage of a plurality of registers into which the instruction is stored. [Embodiment] FIG. 1 is a time chart of control related to fetching of a machine language instruction according to an embodiment of the present invention, where a indicates the case of the above-mentioned instruction A, and b indicates the case of the instruction B. 8 to 14 are the same as in FIG. 4. Explaining the case of instruction A using FIG. 1a, the instruction A is
The operand is _R1 and the second operand is _R2 . And saying that the first operand is R ₁ means that
You won't know until you decode the opcode (OP-A). On the other hand, in this type of instruction, the first operand is
Limited to R ₁ or B×D. Already the third
As explained with the figures, _R1 is to be stored in the fetch register FR3 and B×D is to be stored in the fetch register FR1. Therefore, in this embodiment, as shown in FIG. 1a, the first
The operand is fetched and stored in fetch registers FR1 and FR3 at the same time. Next, by the time you fetch the second operand, the opcode has already been decoded and
Since it is known that it is R ₂ , this is stored in the fetch register FR2. Such control eliminates blank time for fetch operations, which is the case in the prior art, and improves processing speed. The same applies to instruction B in FIG. 2b, in which case the first fetched data of the first operand is also stored simultaneously in fetch registers FR1 and FR3. When the second operand is fetched, the operation code has already been decoded and it is known that this is _R1 , so this is stored in the fetch register FR3. As a result of such control, the first operand B×D of instruction B is stored in the fetch register FR1, and the second operand _R1 is stored in the fetch register FR3. In each of the above embodiments, the case where the fetch register to store the first operand is limited to FR1 or FR3 is explained, but if it is not known at all which register to use, when fetching the first operand, It is sufficient to store the operation code in all registers other than the fetch register FR0 at the same time. [Effects of the Invention] As described in detail above, according to the method of the present invention, the instruction fetch operation is completed one cycle faster than in the conventional method. If the conventional execution time for a certain machine language instruction was 5 cycles including the instruction fetch, this can be shortened to 4 cycles by adopting the control method of the present invention. % speed improvement can be expected. The present invention is particularly effective in the case of an information processing apparatus that employs a microprogram system and whose microinstruction cycle is not faster than the instruction fetch cycle.

[Brief explanation of the drawing]

FIG. 1 is a time chart showing control related to fetching of machine language instructions in one embodiment of the present invention, FIG. 2 is a diagram showing an example of the format of a machine language instruction, and FIG. 3 is a diagram showing an example of an instruction fetch register. FIG. 4 is a time chart showing conventional control related to fetching of machine language instructions. 1...Operation code, 2...First operand, 3...Second operand, 4-7...Fetch register, 8...
Fetch timing, 9...Fetch movement, 10~
13... Timing at which data is stored in the fetch register, 14... Operation of microinstruction.

Claims (1)

[Scope of Claims] 1. A microprogram type information processing device that sequentially fetches each part of a machine language instruction consisting of an operation code part and at least one operand part, and stores each part in a register for each purpose for processing. When the fetch timing for the first operand arrives when fetching a word instruction, the instruction is executed before the decoding result of the operation code for determining which of the application-specific registers the fetch data should be stored in is obtained. A machine language instruction preprocessing method characterized in that the fetch data is simultaneously stored in a plurality of registers among other registers in which it is determined that the fetch data is stored in one of the registers in the instruction format.