JPH0457325A - Plasma treating equipment - Google Patents

Plasma treating equipment

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Publication number
JPH0457325A
JPH0457325A JP16667390A JP16667390A JPH0457325A JP H0457325 A JPH0457325 A JP H0457325A JP 16667390 A JP16667390 A JP 16667390A JP 16667390 A JP16667390 A JP 16667390A JP H0457325 A JPH0457325 A JP H0457325A
Authority
JP
Japan
Prior art keywords
plasma
current
electrode
substrate
exposed part
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16667390A
Other languages
Japanese (ja)
Inventor
Yutaka Omoto
豊 大本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP16667390A priority Critical patent/JPH0457325A/en
Publication of JPH0457325A publication Critical patent/JPH0457325A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To enable the plasma treatment without damaging an insulating film, by arranging an exposed part on the outer periphery so as to come into contact with plasma, in the state that a substrate to be treated is arranged on an electrode, and forming a bypass circuit for making a current flowing from the exposed part flow to the earth. CONSTITUTION:In the state that a substrate to be treated is arranged on an electrode 301 on which the substrate 306 to be treated is arranged, an exposed part 302 is so formed on the outer periphery that the electrode 301 comes into DC contact with plasma. Circuits 303-305 which are connected with the electrode 301 and bypass a current are equipped. The exposed part 302 on the outer periphery collects superfluous electron current in the outer peripheral part of plasma. The current bypass circuits 303-305 make the collected current flow to the earth side via the electrode 301, thereby preventing said current from flowing to the semiconductor substrate 306 side. Hence the deterioration of breakdown strength and the dielectric breakdown of a very thin insulating film can be prevented.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、プラズマ処理Mlに関し、特に非常に薄い絶
縁膜を有する半導体基板を処理するのに最適なプラズマ
処理装置に関するもめである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to plasma processing M1, and particularly to a plasma processing apparatus that is optimal for processing a semiconductor substrate having a very thin insulating film.

〔従来の技術〕[Conventional technology]

従来の装置は、例えば、特開昭63−23750号公報
に記載のように半導体基板上の非常に薄い絶縁膜である
ゲート酸化膜のプラズマ処理による耐圧劣化あるいは絶
縁破壊を、磁場強度を低下させるなどして防止していた
。
Conventional devices, for example, reduce the strength of the magnetic field to prevent breakdown voltage or dielectric breakdown due to plasma treatment of a gate oxide film, which is a very thin insulating film on a semiconductor substrate, as described in Japanese Patent Application Laid-Open No. 63-23750. This was prevented by doing things like this.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上記従来技術は、プラズマ処理速度を低下させたりする
などの問題点があった。
The above-mentioned conventional technology has problems such as a reduction in plasma processing speed.

本発明の目的は処理速度などに直接影響を与える、プラ
ズマ処理条件の変更を行うことなく、半導体基板上の非
常に薄い絶縁膜の耐圧劣化を防止できるプラズマ処理装
置を提供することにある。
An object of the present invention is to provide a plasma processing apparatus that can prevent breakdown voltage deterioration of a very thin insulating film on a semiconductor substrate without changing plasma processing conditions, which directly affects processing speed and the like.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的のために、被処理基板の設置される電極に被処
理基板を設置した状態で電極が直流的にプラズマに接触
するように外周部に露出部分を設け、また、電極に接続
された、電流をバイパスする回路を設けた。
For the above purpose, an exposed portion is provided on the outer periphery so that the electrode contacts the plasma in a DC manner when the substrate to be processed is installed on the electrode, and an exposed portion is connected to the electrode. A circuit was provided to bypass the current.

〔作   用〕[For production]

外周部の露出部分はプラズマ外周部にみろ余剰な電子電
流を収拾し、電流バイパス回路はこれを電極を介してア
ース側に流し、半導体基板側に流れるのを防止する働き
をする。
The exposed portion of the outer periphery collects excess electron current from the plasma periphery, and the current bypass circuit functions to flow this to the ground side via the electrode and prevent it from flowing to the semiconductor substrate side.

これによって半導体基板中の非常に薄い絶縁膜の耐圧劣
化および絶縁破壊を防止することができる。
This makes it possible to prevent breakdown voltage deterioration and dielectric breakdown of the very thin insulating film in the semiconductor substrate.

〔実 施 例〕〔Example〕

以下、本発明の一実施例を第1図により説明する。第1
図は、プラズマにより半導体基板を処理するプラズマド
ライエツチング装置に、高速処理のために磁場を印加し
たものの断面図であり、本発明による絶縁膜に対する耐
圧劣化防止回路を加えたものである。反応客器101は
ガス導入孔102と排気孔103を持ち、反応性ガスを
導入しながら排気することによって定常の低圧雰囲気に
保持されている。被処理物である半導体基板104を載
置するカソード電極105は、カップリングキャパシタ
ー108、マプチングボックス109を介して高周波電
#110に接続されている。
An embodiment of the present invention will be described below with reference to FIG. 1st
The figure is a cross-sectional view of a plasma dry etching apparatus for processing semiconductor substrates using plasma, to which a magnetic field is applied for high-speed processing, and in which a voltage resistance deterioration prevention circuit for an insulating film according to the present invention is added. The reactor vessel 101 has a gas introduction hole 102 and an exhaust hole 103, and is maintained in a steady low-pressure atmosphere by exhausting the reactor gas while introducing it. A cathode electrode 105 on which a semiconductor substrate 104, which is an object to be processed, is placed is connected to a high frequency power source #110 via a coupling capacitor 108 and a mapping box 109.

カソード電1i105は絶縁物106からなる支持材に
よって反応容器101に取り付けられている。
The cathode electrode 1i105 is attached to the reaction vessel 101 by a supporting material made of an insulator 106.

アノード電極107との間に高周波電源110によって
高周波電界を導入すると放電によりプラズマが発生し、
半導体基板104はエツチング加工される。磁場は磁石
ユニvト111により発生され、反応室内に導入される
。
When a high frequency electric field is introduced between the anode electrode 107 and the high frequency power source 110, plasma is generated due to discharge.
The semiconductor substrate 104 is etched. A magnetic field is generated by a magnet unit 111 and introduced into the reaction chamber.

以上は通常のドライエツチング装置の動作を説明したも
ので、以下、本発明が絶縁膜に発生する損傷を低減させ
る効果について実施例の説明を行う。
The above is a description of the operation of a normal dry etching apparatus, and below, an explanation will be given of an embodiment of the effect of the present invention in reducing damage occurring to an insulating film.

第2図はプラズマの持つ電流−電圧特性と本発明を用い
ないli置での動作を示したもので、電極全体の範囲の
プラズマの特性を曲線201、電極中心よりの、局所の
範囲のプラズマの特性を202の曲線で示す。プラズマ
特性の空間分布によって通常このような特性差が生じる
。この時、ウェハは点203で示される電位にあり、曲
線202の特性を持つプラズマ付近に位置する半導体基
板上の絶縁膜には点2041点203の間の電位差が印
加されることになる。
Figure 2 shows the current-voltage characteristics of plasma and the operation in an Li setting without using the present invention. The characteristics are shown by curve 202. Such property differences usually arise due to the spatial distribution of plasma properties. At this time, the wafer is at a potential indicated by point 203, and a potential difference between points 2041 and 203 is applied to the insulating film on the semiconductor substrate located near the plasma having the characteristic of curve 202.

第3図は本発明を実施するためのハードウェアの詳細を
示したものである。301は第1図にもあるカソード電
極で、半導体基板306の周辺にプラズマへの露出部分
302を持つ。302にはプラズマからの電流を導きや
すくするため、突起部を設けている。303.304.
305は余剰な分子電流をバイパスするための回路を構
成する部品で、コイル304、可変抵抗器303、コン
デンサー305からなる。コイル304、コンデンサー
305は高周波電流が流れるのを阻止するためのもので
ある。
FIG. 3 shows details of the hardware for implementing the invention. Reference numeral 301 denotes a cathode electrode, which is also shown in FIG. 1, and has a portion 302 exposed to plasma around a semiconductor substrate 306. 302 is provided with a protrusion in order to facilitate the conduction of current from the plasma. 303.304.
305 is a component that constitutes a circuit for bypassing excess molecular current, and is composed of a coil 304, a variable resistor 303, and a capacitor 305. A coil 304 and a capacitor 305 are used to prevent high frequency current from flowing.

第4図はll83図の回路を動作させた時の電流−電圧
特性上での動作点を示すものである。直線401は調整
後の可変抵抗器の値を示すものである。
FIG. 4 shows the operating points on the current-voltage characteristics when the circuit shown in FIG. 1183 is operated. A straight line 401 indicates the value of the variable resistor after adjustment.

可変抵抗器により、プラズマからの点402−403の
間にある余剰な電子電流は可変抵抗器を介してアースに
バイパスされ、絶縁膜に流れようとする電流は、最大で
点402−404の間の太さにすぎず、最大電圧も点4
05−406の間の大きさにすぎない。
Due to the variable resistor, excess electron current from the plasma between points 402 and 403 is bypassed to the ground via the variable resistor, and the current that attempts to flow into the insulating film is at most between points 402 and 404. The maximum voltage is also point 4.
The size is only between 05-406.

実際に、非常に薄い絶縁膜の一種であるゲート酸化膜を
有する半導体基板(ウェハ)を第1図に示す装置でエプ
チングした場合の本発明の効果について実験例を示す。
An experimental example will be shown to demonstrate the effect of the present invention when a semiconductor substrate (wafer) having a gate oxide film, which is a type of very thin insulating film, is actually etched using the apparatus shown in FIG.

第5図は、エツチング処理後のゲート酸化膜の耐圧を測
定した結果を示すもので、網がかけである領域のゲート
酸化膜は絶縁破壊している。抵抗を接続せず(抵抗値=
00)、露出部もない場合は、第5図(a)に示すよう
にウェハの中心から周辺にかけて絶縁破壊が発生し、破
壊率は53チにも達する。これは第2図で示した電位差
がゲート酸化膜の耐圧を越え、電流が流れたため絶縁破
壊が発生したと考えられる。次に、抵抗値を可変抵抗に
よって50にΩとし、露出部をなしとした場合は、第5
図(b)に示すように周辺部では絶縁破壊が発生したが
、破壊率は15%に減少した。中心部の破壊がなくなっ
たのは、余剰な電子電流をアースに逃がし、発生する電
位差が破壊のスレシ冒ルド以下になったからである。
FIG. 5 shows the results of measuring the withstand voltage of the gate oxide film after the etching process, and the gate oxide film in the shaded area has dielectric breakdown. Without connecting a resistor (resistance value =
00), when there is no exposed part, dielectric breakdown occurs from the center to the periphery of the wafer, as shown in FIG. 5(a), and the breakdown rate reaches as high as 53 inches. This is thought to be because the potential difference shown in FIG. 2 exceeded the withstand voltage of the gate oxide film, and a current flowed, causing dielectric breakdown. Next, if the resistance value is set to 50 Ω using a variable resistor and there is no exposed part, the fifth
As shown in Figure (b), dielectric breakdown occurred in the peripheral area, but the breakdown rate was reduced to 15%. The reason why there was no destruction at the center was because the excess electron current was released to the ground, and the resulting potential difference became below the destruction threshold.

周辺部でなお絶縁破壊が発生しているのは、余剰な電子
電流がウェハを介してアースに流れているからである。
The reason why dielectric breakdown still occurs at the periphery is that excess electron current is flowing through the wafer to ground.

可変抵抗の値を50にΩ、霧出部も設けた場合は、第5
図(C)に示すように周辺に流れる電流はウェハを介さ
ずに流れるようになり絶縁破壊は全く発生しなくなった
。
If the value of the variable resistance is set to 50Ω and a mist outlet is also provided, the fifth
As shown in Figure (C), the current flowing around the wafer now flows without passing through the wafer, and no dielectric breakdown occurs at all.

以上説明した効果は他のプラズマ処理装置でも得ること
ができる。第6図は有磁場マイクロ波ドライエツチング
装置で第1図も同様の手段で所定のガス雰囲気に保持さ
れた反応容器601ヘマグネトロン602によって発生
したマイクロ波を導入し、同時に電磁コイル603によ
って磁界を与えることによりプラズマを生成し、テーブ
ル604上に設置された基板605をエツチング処理す
るものである。テーブル604にはエツチング特性制御
の目的で高周波電源606によって高周波バイアスが導
入される。この装置の場合導入マイクロ波電界強度や高
周波バイアスの不均一で、空間的なプラズマ特性の分布
が生じ、例えエツチング速度が均一であっても上記した
プラズマドライエツチング装置と同様に電流−電圧特性
の不均一が生ずる。このことによって絶縁膜に耐圧劣化
な発生させる場合があり、607に示すバイパス回路と
608に示すテーブル上に設けた突起部で同様の原理に
より、耐圧劣化を防止できる。なお、バイパス回路の構
成は本実施例に限ったものではなく可変抵抗器の代わり
にトランジスターなども用いることができる。要するに
一定電流を流すことのできる回路ならば代替可能である
。
The effects described above can also be obtained with other plasma processing apparatuses. FIG. 6 shows a magnetic field microwave dry etching device, and in the same manner as shown in FIG. This generates plasma and etches the substrate 605 placed on the table 604. A high frequency bias is introduced into the table 604 by a high frequency power supply 606 for the purpose of controlling etching characteristics. In this equipment, the introduced microwave electric field strength and high frequency bias are non-uniform, resulting in a spatial distribution of plasma characteristics, and even if the etching rate is uniform, the current-voltage characteristics will vary as in the plasma dry etching equipment described above. Non-uniformity occurs. This may cause deterioration of the withstand voltage in the insulating film, and the deterioration of the withstand voltage can be prevented by the bypass circuit shown at 607 and the protrusion provided on the table shown at 608 based on the same principle. Note that the configuration of the bypass circuit is not limited to this embodiment, and a transistor or the like may be used instead of the variable resistor. In short, any circuit that can flow a constant current can be replaced.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、絶縁膜を損傷することなく半導体基板
等をプラズマ処理できるので半導体素子を効率よ曵生産
できる効果がある。
According to the present invention, a semiconductor substrate or the like can be plasma-treated without damaging an insulating film, so that semiconductor devices can be efficiently produced.

【図面の簡単な説明】[Brief explanation of drawings]

’4!1図は、本発明の一実施例のプラズマドライエツ
チング装置の要部縦断面図、第2図は、本発明を用いな
い場合の電流−電圧特性上での動作図、第3図は、本発
明を実施するためのハードウェア構成図、!l!4図は
、本発明を実施した場合の電流−電圧特性上の動作図、
′!IA5図は、耐圧測定結果の模式平面図、第6図は
、本発明の他の実施例の有磁場マイクロ波ドライエプチ
ング装置の要部縦断面図である。 303・・・・・・可変抵抗器、302・曲・電流収集
のM/  図 1α− 没辰G器 カソード“ril極 オ Z 図 第 図 ボンデ>サー 第5 ネコ  ケ:トき邑表馴C屹廉 −ヶじトJヒJ永系央壊<f’ 図 (α) (b) (C)
4! Figure 1 is a longitudinal cross-sectional view of a main part of a plasma dry etching apparatus according to an embodiment of the present invention, Figure 2 is an operational diagram in terms of current-voltage characteristics when the present invention is not used, and Figure 3 is a hardware configuration diagram for implementing the present invention! l! Figure 4 is an operational diagram of current-voltage characteristics when the present invention is implemented;
′! Figure IA5 is a schematic plan view of the results of pressure resistance measurement, and Figure 6 is a vertical cross-sectional view of a main part of a magnetic field microwave dry etching apparatus according to another embodiment of the present invention. 303...Variable resistor, 302, song, current collection M/ Figure 1 α- Immersive G device cathode "ril pole O Z diagram Diagram Bonde > Sir No. 5 Neko Ke: Tokimura surface familiar C Figure (α) (b) (C)

Claims (1)

【特許請求の範囲】 1、半導体基板等を処理するプラズマ処理装置において
、被処理基板の置かれた電極に被処理基板が設置された
状態で該電極が直流的にプラズマに接触するように外周
部に露出部分を設けるとともに、該部分から流入する電
流をアースに流すためのバイパス回路を設けたことを特
徴とするプラズマ処理装置。 2、前記バイパス回路が高周波阻止回路、可変抵抗器か
らなる第1請求項に記載のプラズマ処理装置。
[Scope of Claims] 1. In a plasma processing apparatus for processing semiconductor substrates, etc., the outer periphery of the electrode is set so that the electrode is placed in direct current contact with plasma when the substrate is placed on the electrode. What is claimed is: 1. A plasma processing apparatus characterized in that an exposed part is provided in the part of the plasma processing apparatus, and a bypass circuit is provided for causing current flowing from the part to flow to ground. 2. The plasma processing apparatus according to claim 1, wherein the bypass circuit comprises a high frequency blocking circuit and a variable resistor.
JP16667390A 1990-06-27 1990-06-27 Plasma treating equipment Pending JPH0457325A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16667390A JPH0457325A (en) 1990-06-27 1990-06-27 Plasma treating equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16667390A JPH0457325A (en) 1990-06-27 1990-06-27 Plasma treating equipment

Publications (1)

Publication Number Publication Date
JPH0457325A true JPH0457325A (en) 1992-02-25

Family

ID=15835604

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16667390A Pending JPH0457325A (en) 1990-06-27 1990-06-27 Plasma treating equipment

Country Status (1)

Country Link
JP (1) JPH0457325A (en)

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