JPH0457370A - Electrostatic inductive semiconductor element suited to pressure-welded package structure - Google Patents

Abstract

PURPOSE:To relatively easily erect the pressure-welded structure comprising a plane gate type electrostatic inductive thyristor and a transistor for making use of a mesa type element structure for the pressure-welded package structure by arranging a segment cathode electrode on the mesa type part. CONSTITUTION:Exceeding two each of plane gate type unit elements are arranged on the mesa type part on one surface of a semiconductor substrate 1; a segment cathode electrode 10 is provided on the insulating thin film coated surface in the outer peripheral region of gate regions 2 and cathode region 3; and the gate regions 2 are provided on the parts encircling the mesa type part further to be connected with a segment gate electrode. Besides, multiple segmets are arranged in the same semiconductor substrate 1 and then the cathode electrode 10 is pressure-welded so as to be Parallel-connected with the segments. Through these procedures, the cathode electrode 10 located on the mesa type part making the step difference from the gate electrode can avoid the contact with the gate electrode during the pressure-welding process, thereby enabling the larger spaced structure to be erected relatively easily.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a planar gate type static induction transistor (S
tatic induction
r; S I T ) and thyristor (Static I
duction Thyristor; S I Th
The present invention relates to a device embodying a method for increasing the area and current capacity of ), and specifically relates to an electrostatic induction type semiconductor element suitable for a press-contact type package structure.

[Conventional technology]

Conventionally, as electrostatic induction type semiconductor devices, buried gate type SIT and SI thyristor, planar gate type SIT and SI thyristor have been proposed. The buried gate type structure is suitable for high breakdown voltage and large current capacity, so by adopting a pressure contact structure, devices of several kV and several hundred A class have been realized.

On the other hand, in order to suppress the drop in yield due to the necessity of microfabrication technology for planar gate type SIT or SI Sirisk, the current capacity is several tens of A as an individual device.
By forming these into a multi-chip hybrid configuration, devices of several hundred A class have been realized.

However, the device breakdown voltage has so far been about 100 OV, and the package structure has been one that is suitable for cooling only one side (the back side) made of bonding ink rather than a press-contact type. One of the reasons for this is that no pressure-contact packaging technology has been developed to accommodate the fine structure of the gate electrode structure unique to planar gates, and because planar gate structures have better high-frequency characteristics than buried gate structures. Rather, the reason was to adopt a package with better high-frequency performance in order to pursue high speed. However, recent power semiconductor devices are pursuing high frequency and high-speed switching performance as well as larger capacity and higher voltage resistance, and even electrostatic induction type semiconductor devices, which have extremely excellent performance in these respects, are not suitable for planar gates. There is a strong need to aim for higher voltage, higher capacity, and higher capacity (with a new planar gate structure and a pressure welding structure to maintain the cooling performance required for large current and high voltage elements). There is an increasing need for electrostatic induction type semiconductor devices having the following characteristics.

Traditionally, pressure welding structures have the following features compared to soldering and wire-bond structures.

■ Cooling effect is great because it is double-sided cooling.

■ Less thermal distortion due to the difference in thermal expansion coefficient between the semiconductor element and the case. Therefore, it is possible to increase the area of semiconductor elements.

Therefore, a pressure contact type structure is suitable for increasing the current capacity.

However, as mentioned above, electrostatic induction type semiconductor elements having a planar gate structure still have a medium capacity, and a press-contact type structure has not been realized due to the pursuit of high speed. Therefore, a press-contact structure is essential for achieving high breakdown voltage and large current capacity, and the need for planar gate electrostatic induction type semiconductor elements applicable to press-contact package structures is increasing.

[Problem to be solved by the invention]

The purpose of the present invention is to provide a static induction type semiconductor device suitable for a pressure contact type package structure, which embodies a method of applying a pressure contact structure used in large current capacity SIRISK etc. to a planar gate type static induction type semiconductor element. The goal is to provide the following.

[Means to solve the problem]

(1) Two or more planar gate type unit elements are arranged in a mesa-shaped portion on one surface of a semiconductor substrate. Segment cathode electrodes are provided on surfaces on which insulating thin films are provided in the outer peripheral regions of the gate region 2 and cathode region 3.

A gate region 2 is provided in a portion surrounding the mesa-shaped portion and further connected to a segment gate electrode.

(2) A plurality of the above segments are arranged within the same semiconductor substrate.

(3) Press the cathode electrodes 10 so that the segment cathode electrodes are connected in parallel.

Since the segment cathode electrode is located in a mesa-shaped portion, there is a difference in level from the segment gate electrode, and the cathode electrode is prevented from coming into contact with the gate electrode when pressed. Therefore, it is relatively easy to increase the area.

The structure of the present invention is as shown below. That is, the present invention provides a planar gate type structure in which a gate region 2 of a second conductivity type surrounds a cathode region 3 of a first conductivity type in a mesa portion near the surface of a semiconductor substrate l of a first conductivity type. At least two or more unit elements of electrostatic induction type semiconductor elements are arranged, an insulating thin film 8 is arranged on the outer periphery of the gate region 2 and the cathode region 3, and a segment cathode electrode 6 is provided to connect the cathode regions 3 in parallel, A gate region 2 of a second conductivity type and a segment gate electrode 7 are arranged around the mesa portion, and an anode region 4 and an anode electrode 5 are arranged on the back surface of the semiconductor substrate 1 to form a segment, A cathode 10 in which a plurality of segments are arranged in parallel and segment cathode electrodes 6 are connected in parallel.
are pressed together, and the segment gate electrodes are connected to each other, and the gate 11 is pressed at the periphery of the gate electrode 9, and the segment anode electrode 5 is connected to the anode 1 by pressure contact or an alloy.
It has a configuration as an electrostatic induction type semiconductor element suitable for a pressure contact type package structure, which is characterized in that it is connected to 2.

〔Example〕

FIG. 1 is a schematic cross-sectional structural diagram of an electrostatic induction type semiconductor element adapted to a press-contact package structure according to the present invention.
Figure (a) shows an example of pattern arrangement in which the element structure of the embodiment shown in Figure 1 is arranged radially in the longitudinal direction or radial direction of the cathode segment.

Furthermore, FIG. 2(b) shows the element structure in a cross section taken along one radial direction AA' in FIG. 2(a).

As shown in FIG. 1, two or more planar gate type unit elements are arranged in a mesa-shaped portion on one surface of a semiconductor substrate 1. That is, in FIG. 2, the gate region 2 is formed including the side wall portion 20 of the mesa. The etching depth of the mesa is usually several μm to 10-odd μm. A segment cathode electrode 6 is provided on the surface on which an insulating thin film 8 is provided in the outer peripheral region of the gate region 2 and cathode region 3. That is, the segment cathode electrode 6 does not come into contact with the gate region 2 formed on the mesa plateau through the insulating thin film.

A gate region 2 is also provided in a portion surrounding the mesa-shaped portion and further connected to a segment gate electrode. That is, the gate electrode is formed in the gate region 2 below the mesa plateau, and the gate electrode is not in direct contact with the gate region 2 inside the mesa plateau.

A plurality of the above segments are arranged within the same semiconductor substrate.

That is, at least two or more unit elements are arranged within a mesa-shaped plateau, and by forming a plurality of such mesa shapes as multi-channel shapes, the current capacity can be adjusted.

The cathode electrodes 10 are pressed together so that the segment cathode electrodes 6 are connected in parallel.

Since the segment cathode electrode 6 is located on a mesa-shaped plateau, there is a step difference between the segment gate electrode 7 and the segment gate electrode 7 by a step bone due to mesa etching, and it is possible to prevent the cathode electrode from coming into contact with the gate electrode when pressed. Therefore, it is relatively easy to increase the area. In other words, it is possible to take out the electrodes as described above while maintaining the planar gate structure.
An electrostatic induction type semiconductor device suitable for a pressure contact type package structure has been provided.

When spin-coding photoresist, the in-plane thickness can be easily made uniform, making it easy to microfabricate mesa parts, so the embodiments of the present invention are characterized in that even planar structures can be manufactured with high yield. It is something.

〔Effect of the invention〕

According to the element structure of the electrostatic induction type semiconductor device suitable for the pressure contact type package structure according to the present invention, since the mesa shape is utilized, it is relatively easy to make the planar gate type electrostatic induction type silicon risk and transistor into the pressure contact structure. Become.

In contrast to conventional devices in which the gate and cathode have a wire-bonded structure, which is cooled on one side, the device of the present invention can be cooled on both sides, so the cooling effect is large, and the capacity can therefore be increased.

Since a planar gate type electrostatic induction semiconductor element has good turn-on characteristics, by increasing the area using a pressure contact structure, it becomes possible to turn on a large current at high speed.

Furthermore, the pressure contact structure is highly compatible with planar gate type semiconductor devices (this makes it possible to achieve higher current and larger area while maintaining the high frequency and high speed switching performance of planar gate type electrostatic induction type semiconductor devices). It also has the advantage of

[Brief explanation of the drawing]

FIG. 1 is a perspective sectional view showing the basic structure of the segment of the present invention, and FIGS. 2(a) and 2(b) are diagrams illustrating the present invention in detail. ) is a radial cross-sectional view. I...High resistance semiconductor substrate, 2...
...Gate region, 3...Cathode region, 4...Anode region, 5...Anode electrode, 6... ...Segment cathode electrode, 7...
・・・・・・Segment gate electrode, 8・・・・・・
...Insulating thin film, 9...Gate electrode, IO...Cathode electrode, 11...Peripheral gate, 12...Alloy anode electrode, 20...Side wall patent applicant Toyo Denki Seizo Co., Ltd.

Claims (1)

[Claims] (1) A planar gate-type electrostatic capacitor in which a gate region 2 of a second conductivity type surrounds a cathode region 3 of a first conductivity type in a mesa portion near the surface of a semiconductor substrate 1 of a first conductivity type. At least two or more unit elements of inductive type semiconductor elements are arranged, an insulating thin film 8 is arranged on the outer periphery of the gate region 2 and the cathode region 3, and a segment cathode electrode 6 is provided to connect the cathode regions 3 in parallel, and the mesa A gate region 2 of a second conductivity type and a segment gate electrode 7 are arranged around the portion, and an anode region 4 and an anode electrode 5 are arranged on the back surface of the semiconductor substrate 1 to form a segment. A cathode 10 in which a plurality of segment cathode electrodes 6 are arranged in parallel and connected in parallel.
are pressed together, and the segment gate electrodes are connected to each other, the gate 11 is pressed at the periphery of the gate electrode 9, and the segment anode electrode 5 is connected to the anode 1 by pressure contact or an alloy.
1. An electrostatic induction type semiconductor element adapted to a pressure contact type package structure, characterized in that the element is connected to a pressure contact type package structure.