JPH0457577A - Picture signal reduction device - Google Patents

Abstract

PURPOSE:To generate a reduced picture with fidelity to an original signal by applying reduction processing by a reduction circuit to a picture element series doubling equivalently a sampling frequency by means of an interpolation circuit. CONSTITUTION:A sampling means 11 samples an input analog picture signal to eliminate reflected distortion caused in the reduction by a digital filter 12 and a picture selected in response to a desired reduction rate at a reduction circuit 13 and a variable coefficient are multiplied and the result is stored in a picture memory and then read and a picture reduced by the desired reduction rate is displayed on the screen. An interpolation circuit 14 applies interpolation processing doubling equivalently the sampling frequency in comparison with a time series synthesis series of an output picture element of the sampling means 11. Thus, an accurate and sharp reduced picture is obtained.

Description

[Detailed Description of the Invention] [Summary] Regarding a device that reduces an image signal at a desired reduction rate, the purpose is to create a reduced image signal that is more faithful to the original signal. The resulting time-series composite series of pixels is supplied to a reduction circuit through a digital filter for removing aliasing distortion that occurs during reduction, and the reduction circuit reduces the desired reduction from among the output pixels of the digital filter. In the image signal reduction device that multiplies the selected pixel by a variable coefficient according to the desired reduction ratio, stores the multiplication result in an image memory and reads it out to display an image reduced at the desired reduction ratio on the screen, the sampling means An interpolation circuit is provided in the middle of the signal path from the output end of the circuit to the input end of the reduction circuit to equivalently double the sampling frequency compared to the time-series composite series of output pixels of the sampling means. Configure.

[Industrial application field]

The present invention relates to an image signal reduction apparatus, and more particularly to an apparatus for reducing an image signal at a desired reduction ratio.

Image signals such as television signals may be reduced and displayed on a screen as necessary. In this case, it is necessary to display an image with a desired reduction ratio more faithfully to the original signal.

[Prior Art] FIG. 6 shows a block diagram of an example of a conventional signal reduction device. In the figure, an analog image signal indicated by I in FIG. 7(A) inputted to the input terminal 1 is supplied to the A/D conversion circuit 2,
Here, the signal is analog-to-digital converted into a digital image signal.

This digital image signal is a signal obtained by sampling an analog image signal at a constant period T, and is supplied to a digital low-pass filter (LPF) 3 in order to avoid aliasing distortion that occurs during reduction processing, which will be described later. , its high frequency components are attenuated.

The cutoff frequency of this digital LPF 3 is defined as (x (m)l) when the image signal sequence is (t, m..., -
2, -1, 0, 1, 2, ...), the reduced image signal sequence (xd
(m)) or (xd (m) l = (x (mM)
If it is expressed as 1, then it is expressed as 1/(2MT).

The digital image signal (hereinafter also referred to as 9 pixels) taken out from the digital LPF 3 is supplied to the multiplier 6 through registers 4 and 5, which are connected in cascade in two stages, respectively.
It is supplied to the multiplier 7 through the register 4. register 4
and 5 delay the input digital image signal by one sampling period. Therefore, the multiplier 6 receives the pixel A delayed by 2 sampling periods, and the multiplier 7 receives the pixel B delayed by 1 sampling period.

Multipliers 6 and 7 are circuits that multiply the pixels A and B described above by the coefficients (1-Z) and Z from the control circuit 8, respectively.

Here, the coefficient Z is the output order of the reduced output image as n,
When the reduction rate is 1/D, this is the decimal part of the numerical value expressed as D-n. Therefore, the above coefficient (1-Z) and Z are not constant values, but values that change depending on the order of output pixels and the like. The output signals of the multipliers 6 and 7 are supplied to an adder 9, where they are added together to form one pixel of a reduced image, and then input to an image memory 11 via a register 10.

A write operation of the image memory 11 is controlled by a write address and a write pulse from the control circuit 8, and a read operation is controlled by a read address and a read pulse. Pixels of the reduced image are sequentially read out from the image memory 11.

Now, an example will be explained in which the image is reduced to 1/3.2. At this time, since the output pixel (indicated by a in FIG. 7A) in the first order (assuming n=0) has the coefficient Z or "0", the multiplier 6, the adder 9, register 1
The value is written to the image memory 11 as it is through 0. The write address at this time is "0" as shown in FIG. 7(E). Further, the vertical broken line in FIG. 7(A) indicates the sampling time point, and FIG. 7(B) indicates the order of input pixels (pixel number) indicated by the reference counter in the control circuit 8. ) indicates the numerical value K expressed as D−n, and (D) in the figure shows a coincidence pulse generated within the control circuit 8. When this coincidence pulse is at a high level (ON), the control circuit 8 controls the image memory. A write pulse is sent to 11 to write to the write address shown in FIG. 11 (E).

Therefore, pixels when no write pulse is output are thinned out.

Next, since the above value is r3.2J, input pixel B
is the third input pixel, and its multiplication coefficient Z is "0.2", and the input pixel A is the second input pixel before it, and its multiplication coefficient (IZ) is "0.8". ”, and by adding the respective multiplication outputs in the adder 9, the pixel at the position shown in FIG. is written to address “1”.

Next, since the above value is r6.4J, input pixel B is the 6th input pixel and its multiplication coefficient Z is "0.4", and input pixel A is the 5th input pixel and its multiplication coefficient Z is "0.4". The multiplication coefficient (1-Z) is "0.6", and the address of the pixel or image memory 11 substantially shown at position C in FIG. 7(A) obtained by adding these multiplication results is " 2”.

Thereafter, image information obtained by performing the calculations shown in the following table in the same manner as described above is written into the image memory 11.

As a result, the memory contents and addresses of the image memory 11 become as schematically shown in FIGS. 7(F) and (G), respectively.

Therefore, after writing is completed, by sequentially reading out the image memory 11 from address "0", pixels a,
The pixels b, c, . . . are extracted in this order, and these pixels display an image that is horizontally reduced to 1/3.2 of the original image.

[Invention or problem to be solved]

However, in the conventional apparatus described above, the reduced image is generated by interpolating the input pixels, and the sampling period cannot be made very short due to cost reasons, so the fidelity of the reduced image with the original image may be slightly affected. There was a problem.

The present invention has been made in view of the above points, and an object of the present invention is to provide an image signal reduction device that can create a reduced image signal that is more faithful to the original signal.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, reference numeral 11 denotes a sampling means that samples the input analog image signal. A digital filter 12 is provided to remove aliasing distortion that occurs during reduction. Reference numeral 13 denotes a reduction circuit which stores the multiplication result of the image selected according to the desired reduction rate and the variable coefficient in the image memory and reads it out, and displays the image reduced at the desired reduction rate on the screen.

In this configuration, the present invention provides an interpolation circuit 14 in the middle of the signal path from the output end of the sampling means 11 to the input end of the reduction circuit 13, as shown by a solid line or a broken line in FIG.

Here, the interpolation circuit 14 performs interpolation processing to equivalently double the sampling frequency compared to the time-series composite series of pixels output from the sampling means 11.

[Effect]

In the present invention, since the reduction circuit 13 performs reduction processing on a pixel series whose sampling frequency has been equivalently doubled by the interpolation circuit 14, each pixel of the reduced image to be obtained is It can also be generated using two pixels located closer together.

〔Example〕

FIG. 2 shows a block diagram of one embodiment of the invention.

In the figure, the same components as in FIGS. 1 and 6 are denoted by the same reference numerals, and their explanations will be omitted. In Figure 2, FIR
The (finite impulse response) filter 21 constitutes the interpolation circuit 14 described above.

This FIR filter 21 has, for example, a direct type structure as shown in FIG.

In FIG. 3, 31. 3112 are 12 registers, each having a delay time of one sampling period, and are connected in series. Also, register 31. The input data (pixels) of the register 31.6 and the output data (pixels) of the register 31.6 are combined in an adder circuit 321, and then multiplied by a coefficient h1-1 in a multiplier 33. Further, the output signal of the register 316 is multiplied by a coefficient h6 in a multiplier 33□.

Here, the coefficient of each multiplication above. -h 12 is set, for example, to the following locations.

h o = h + z = 4.917632 02. h+
= h 1+=5.42556E 02. hs
=b+. =-6,68198E-02,h3 =h,
=-7,22953B-02,h, =h, =5.
17809E-02, hs=h7=0.316125.
hs =0.431725 multiplier 33. above. ~337
The respective output signals are commonly input to the adder circuit 34, where they are added and combined and then taken out as output data. Note that the coefficients h7 to h12 above are the registers 317 to 311.
Indicates the coefficient by which each output signal of 2 is to be multiplied.

The FIR filter 21 having such a configuration is a digital filter of a direct type configuration, and the analog image signal shown at 1 in FIG. 4(A) is sampled by the A/D conversion circuit 2, and the sampling point is indicated by the broken line in FIG. ), which is passed through the digital LPF 3, and a time-series composite series of pixels is supplied as an input signal. Then, the FIR filter 21 inserts a value "0" between each sampling point (pixel) of this input signal, and generates (interpolates) a value that becomes the inserted "0" by digital filtering. As a result, a digital signal sequence whose sampling frequency is isometrically doubled is extracted from the FIR filter 21, as shown schematically in FIG. This digital signal series shows the original amplitude 1 more accurately, as shown by the square mark in FIG. 5, than the digital signal series before interpolation, shown by the diamond mark in the same figure.

This digital signal sequence is supplied to a multiplier 6 via registers 4 and 5, respectively, and is also supplied to a multiplier 7 via register 4, and is supplied with the coefficient (1-Z) from the control circuit 22.
), Z, are combined in an adder 9, are temporarily stored in a register 10, and then written to an image memory 23. A write operation of the image memory 23 is controlled by a write address and a write pulse from the control circuit 22, and a read operation is controlled by a read address and a read pulse.

Next, data written to and read from the image memory 23 of this embodiment will be explained. The control circuit 22 has a reference counter, and in synchronization with the sampling period of the output digital signal series of the digital LPF 3, the count value is counted up by "1" on the same line as shown in FIG. 4(C), as in the conventional case. To go. The count value of this reference counter indicates the pixel number (NO) indicating the order of input pixels, but as described above, in this embodiment, by digital filtering by the FIR filter 21, the lower part of FIG. Since the value is interpolated at the position indicated by the arrow, the original pixel that has not been interpolated in the first half of one count period of the reference counter is input to the reduction circuit 13, and the interpolated pixel is input in the second half. is input.

In addition, when reducing the pixel to 1/3.2, the control circuit 22 changes the value of the above as shown in FIG. 4(D), and changes the matching pulse (write pulse) as shown in FIG. The write address to the image memory 23 is generated as shown in the figure (
The basic reduction algorithm that is changed as shown in F) is the same as that of the conventional apparatus shown in FIG. 6 described above.

However, in this embodiment, the pixel to be multiplied by the coefficient whose value is less than 0.5 between the coefficient Z indicating the decimal part of the value of K and the other coefficient (1-Z) is the other coefficient. The interpolated pixels are selected because they have less weight compared to the pixels to be multiplied, and the pixels to be multiplied by the other coefficient whose value is greater than or equal to 0.5 are the non-interpolated ones. , and after multiplication and addition, the pixels are stored in the image memory 23.

Therefore, in this embodiment, taking as an example the case where the reduction ratio is 1/3.2, as shown in the table above, the first pixel (output pixel number,
=0), the first input pixel with the reference count value "0" is used as is.

The sampling position of this pixel is indicated by a' in FIG. 4(B), and this pixel is written to address "0" in the image memory 23.

Conventionally, the next output pixel No. = 1 is generated from pixels with reference count values "2' and "3", or in this embodiment, the pixel with the reference count value "3" is generated from the multiplication coefficient Z of the input pixel with reference count value "3". Since the value is less than "0.5", select the interpolated input pixel in the latter half of the reference count value "2" (its sampling position is indicated by b2 in Figure 4 (B)) and multiply it by the coefficient Z. The other pixel is set to the same reference count value “2” as before.
” input pixel that is not interpolated in the first half ((B) of the same figure)
The sampling position is shown as b' in Figure 4 (B) and is multiplied by the coefficient (1-Z). generate a pixel.

The pixel at position b' is at address N of the image memory 23.
Written to J.

Hereinafter, in the same manner as above, C'd'...
- Pixels at sampling positions as shown are sequentially generated by multiplying and adding the interpolated input pixel, the interpolated original input pixel, and each coefficient, respectively, and are stored in the image memory 23. They are written sequentially.

After the writing to the image memory 23 is completed, the contents of the image memory 23 become as schematically shown in FIG.
By incrementing the data by 1 from the image memory 23, the data a', a', and
The pixels are read out in the order of sampling positions indicated by b', C'd', . . . By displaying the pixels read out in this manner on the screen, it is possible to display an image that is reduced to 1/3.2 times the original image. Furthermore, in this embodiment, this reduced image uses interpolated pixels that are closer to the pixels of the reduced image to be generated, so that it is a more accurate and clear image.

Note that the present invention is not limited to the above embodiments; for example, the FIR filter 21 may be provided on the input side of the digital LPF 3, and the interpolation circuit 14 is not limited to the configuration shown in FIG. Of course not.

〔Effect of the invention〕

As described above, according to the present invention, a reduced pixel is generated using two pixels that are located closer to each other than in the past, so it is possible to obtain a reduced image that is more accurate and clearer than in the past. It has the following features.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle configuration of the present invention, Figure 2 is a block diagram of an embodiment of the present invention, and Figure 3 is a diagram of the FI
A configuration diagram of an embodiment of the R filter, FIG. 4 is a time chart for explaining the operation of FIG. 2, FIG. 5 is a diagram comparing signals before and after interpolation, and FIG. An example of a block diagram, FIG. 7 is a time chart for explaining the operation of FIG. In the figure, 6.7 is a multiplier, 11 is a sampling means, 12 is a digital filter, 13 is a reduction circuit, 4 is an interpolation circuit, 1 is an FTP filter, 2 is a control circuit, and 3 is an image memory.

Claims (3)

[Claims] (1) Sampling means (11
) is passed through the reduction circuit (13) through a digital filter (12) for removing aliasing distortion that occurs during reduction of the time-series composite series of pixels obtained by sampling.
The reduction circuit (13) multiplies a pixel selected from among the output pixels of the digital filter (12) by a variable coefficient, and stores the multiplication result in the image memory. In an image signal reduction device that reads out and displays an image reduced at the desired reduction ratio on the screen, the signal path from the output end of the sampling means (11) to the input end of the reduction circuit (13) is provided. , an interpolation circuit (11) that equivalently doubles the sampling frequency compared to the time-series composite series of output pixels of the sampling means (11);
14) An image signal reduction device characterized by comprising: (2) The reduction circuit (13) is connected to the interpolation circuit (14).
2. The image signal reduction apparatus according to claim 1, wherein the first pixel newly generated by the first pixel and the second pixel adjacent thereto are respectively selected and multiplied by the variable coefficient. (3) The image signal reduction device according to claim 1 or 2, wherein the interpolation circuit (14) is a digital filter having a finite impulse response filter direct type configuration.