JPH0457578A - Digital phase controller for rotating body - Google Patents

Abstract

PURPOSE:To prevent deterioration in the accuracy due to digit truncation by converting the digit truncation data caused in a digital phase processing system into a time series signal within a time when a rotating body turns around. CONSTITUTION:The controller consists of a drum motor 1, a rotating speed detector 2, a frequency divider circuit 3, a phase control signal generating means 5, a multiplier 7, a division means 11, a correction means 12, a signal source or FG signal input terminal 13, a level conversion means 14, a signal conversion means 15 and an adder means 16. Then a digit truncation data caused due to a limit of an input bit number of a D/A converter 9 and an input bit number of the adder 16 or the like is corrected simply with high accuracy by using the correction means 12, the level conversion means 14 and the signal conversion means 15 so as to convert the digit truncation component of a phase control data into a time series signal whose time average is equal to the digit truncation component. Thus, the phase control of the rotating body is implemented without deteriorating the control accuracy of the phase control system.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a digital phase control device used for controlling a rotating body.

2. Description of the Related Art In recent years, importance has been placed on speed control and phase control of rotating bodies such as video tape recorders using rotating heads.

FIG. 5 shows the configuration of a digital phase control system that has been conventionally used for controlling rotating bodies. In FIG. 5, the rotation of the drum motor 1 is detected by a rotation detector 2 provided on the drum motor 1. In FIG.

The rotation detector 2 includes a frequency generator and a pulse generator, and is configured so that, for example, 16 pulses of FC pulses having a period corresponding to the rotation speed can be obtained per one rotation of the drum motor 1. The frequency dividing circuit 3 divides the frequency of the FC pulse by the number of pulses (for example, 16) of the FC signal generated during one rotation of the drum motor 1, and generates a phase signal (hereinafter referred to as PC signal) corresponding to the rotational phase of the drum motor 1. ) is obtained at a rate of one per rotation of the drum motor 1. The speed control signal generating means 4 performs speed error detection gain correction, filtering, etc. to calculate digital speed control data VD.

On the other hand, the phase control signal generating means 5 performs phase error detection, gain correction, filtering, etc., and calculates phase control data PD. The speed control data VD multiplied by 1 in the multiplier 6 and the phase control data PD multiplied by 2 in the multiplier 7 are added in the adder 8, and the D/A
A converter 9 converts it into an analog signal. The output of the D/A converter 9 is amplified in a drive amplifier 10, and the drum motor 1 is controlled by this output.

Here, K1. 2 indicates the ratio of the control amount between the speed system and the phase system, and generally Kl)K2 is used to ensure the stability of the system.
As a result, speed control works more strongly than phase control. For example, VD and PD each have 8 bits (a=8),
Assuming that the input bit number d of the D/A converter is 9 bits, K1=
If IK2=2-'=24, the calculation of 1.VD+ and 2.PD performed in the adder 8 results in 13-bit data. However, since the input to the D/A converter is 9 bits, a loss of 4 bits occurs. For this reason, conventionally, the upper 9 bits of the 13-bit data are treated as valid data, and the lower 4 bits are discarded as decimal data, or are rounded up or rounded off.

In this case, the digit loss data consists only of phase control data. In other words, of the phase control data PD, only the upper 4 focuses are used as the effective focus of the phase system (bit number b) as control information for the drum motor 1, and the lower 4 bits (bit number C) are processed as digit loss data. Ru.

Also, if the number of input points e of the adder 8 is 8 bits, then
KI=1. Since 2 = 2', 2 in Bukosoku 7
As a result of the XPD calculation, the phase control data PD becomes data 28 to 24. When the adder 8 performs digit alignment with the speed control data VD, the lower four bits of PD at the input of the adder 8 become digit-off data.

Problems to be Solved by the Invention However, in the above configuration, the precision of the control signal given to the drum motor 1 deteriorates, and wow and flutter occur because the digit loss data is rounded down, rounded up, rounded off, etc. This has negative effects such as an increase in To solve this problem, it is necessary to provide separate D/A converters for speed control data and phase control data, or to
It would be possible to increase the number of input focus points of the A converter 9 or the number of input points of the adder 8, but this is difficult due to problems such as the circuit becomes complicated, accuracy cannot be ensured in D/A conversion, and cost increases. It becomes.

The present invention solves the above-mentioned problem and provides a means for preventing deterioration of accuracy due to loss of digits.

Means for Solving the Problems In order to achieve the above object, the present invention provides a signal source or an FG.
a signal source, a rotational phase detection means for detecting a rotational phase from a signal corresponding to a rotational phase of the rotating body, a phase control signal generation means for processing an output signal of the rotational phase detection means to obtain a phase control signal; dividing means for dividing a phase control signal into an effective component and a lost-digit component of a predetermined number of focuses; a correcting means for generating a correction value from the lost-digit component; value converting means for converting into a series signal; signal converting means for converting the time-series signal into a signal having a time average substantially equal to the decimated component; and adding means for adding the output of the signal converting means and the effective component. The apparatus is characterized in that the output of the adding means is used to control the phase of the rotating body.

According to the above configuration, the present invention converts the digit loss portion of the phase control data into a time series signal whose time average is equal to the digit loss component using the correction means, the value conversion means, and the signal conversion means. It is possible to easily and accurately correct data with digit loss caused by limitations such as the number of input bits of the /A converter and the number of input bits of the adder.

Embodiment Hereinafter, a digital phase control device for a rotating body according to an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention,
Elements that are the same as those shown in FIG. 5 are given the same reference numerals and their explanations will be omitted.

First, the a-bit phase control data PD generated by the phase control signal generating means 5 is given to the dividing means 11. Let b be the effective number of points of focus of the phase system determined by Kl, and 2, then the dividing means 11 divides PD into an effective component of the upper b bits and a lost component of the lower c (=a-b) bits. . The offset component is corrected by the correction means 12 and sent to the value conversion means 14. [Value conversion means] 4 converts one correction value into a time-series signal within a predetermined time (within the time for one rotation of the drum motor l) using a signal from a signal source inputted from the terminal 13 or an FG multiplied signal. . The time-series signal is converted by the signal converting means 15 into a waveform whose time average is equal to the value of the lost component, and is added to the effective component by the adder 16.

FIG. 2 shows a dividing means 11 and a correcting means 1 according to an embodiment of the present invention.
2 and a value conversion means 14 are implemented in hardware. FIG. Furthermore, FIG. 3 shows a method of converting this data.

The phase control data PD of a bit (e.g. 8 bits) is 8
It is applied to the input of the bit AND gate group 201. The other input of the AND gate group 201 is connected to the terminal 202.
The upper b bits (for example, the upper 4 bits) of the phase control data PD
An input (a signal with a focus code of OF OH) is added to extract the focus (focus).

Further, the output of the AND gate group 201, that is, the upper b bits of the phase control data PD, is subtracted from the phase control data PD by an adder 203.

Therefore, the output of the adder 203 is the phase control data P
The lower c of D = a-b bits (4 bits).

The output of the adder 203 is read into the counter 204 every rotation of the drum motor 1. The output of the signal source or the FG multiplied signal is applied to the terminal 13, and the counter 204 is decremented by this signal. In the comparator 205, if the output of the counter 204 is a value of 1" or more, it outputs '1' to the C-th pinto (2' pinot), and if the output of the counter 204 is '0' or less, it outputs '0'. In other words, in this embodiment, the digit loss data is converted into a PWM wave.Furthermore, the counter 204 and the comparator 205
A correction means, a value conversion means, and a signal conversion means are realized.

The output of the AND gate group 201 and the output of the comparator 205 are
The signals are added by an adder 16, passed through a multiplier 7, and inputted to an adder 8.

For example, the speed control data VD and the phase control data PD are each 8 bits (a=8), and the number of nodes d in the D/A converter is
is 9 bits, and K1=1. When 2=2-4, the number of bits of the effective component of the phase system is -4, and the number of bits of the missing component is c=4. In the conventional phase control device, a loss of 4 bits occurs, but with the present invention, the drum motor 1
If the number of pulses of the FC signal or the number of pulses of the signal from the signal source generated during rotation is set to 16, there will be no loss of digits in the phase control data during a predetermined period of time (during one revolution of the drum motor 1). In other words, the number of pulses PN generated from the signal source or FG during one rotation of the drum motor 1
PN may be determined so that the relationship PN=2' holds between C and the number of lost bits C.

Now, assume that PD=(11001010:l, PN=16, and the period of the signal from the signal source or FC signal is TP. If a signal of [111100001 is input from the terminal 202, the output of the AND gate group 201 is [ 110000
001, the output (correction value) of the force U calculator 203 is [0000
1010].

This output is sent to the counter 204 every rotation of the drum motor 1.
is input. Counter 204 is decremented by a signal from terminal 13. The data [000010101] read into the counter 204 at time T in synchronization with the signal input from the terminal 13 is decremented at time T+TP, and becomes [00001,00 hours]. Similarly, time T+
Decrement is performed until 15XTP, and time T+16X
A new preset is performed at TP.

In other words, the correction value was converted into a time-series signal.

Comparator 205 outputs [00010000] only when the value of counter 204 is "1" or more. As a result, comparator 2
The output of 07 is [00
010000] is output, and (00000000) from time T+10XTP to time T+16XTP is output. That is, the time average value during one revolution of the drum motor 1 after being converted into a PWM wave is equal to the value of the digit loss component.

Figure 3 shows the data conversion method at this time.1 For example, speed control data VD9 phase control data PD
are 8 bits each (a-8), the number of input nodes d of the D/A converter is 9 bits, and K1 = IK2 = 24, then the number of bits of the effective component of the phase system b = 4, and the bit of the digit loss component. The number c=4.

Therefore, the PD shown in FIG. 3(a) is divided into the effective component (b) (upper b bits) and the lost component (lower C focus) (c). The precision component of (C) is the value conversion means 1
4 and the signal conversion means 15, for example, 2 shown in (d)
It is converted into a time series signal consisting of only 4 bits. (e)
is the output of the adder 16 (the sum of C1l and (d)). This output is multiplied by 2 (24 times in this embodiment) by the multiplier 7, and becomes as shown in (f).

Normally, a loss of digits would occur at this time, but this is corrected in advance by the value conversion means 14 and the signal conversion means 15. (g) shows the output of the multiplier 6, VDXK1. (f) and (g) are added by the adder 8, resulting in 9-pinto data as shown in (h).

FIG. 4 shows multiplier 61, multiplier 71, dividing means 11° correction means 12. Value conversion means 14. Signal conversion means 15, addition means 1
6 and the addition means 8 are implemented by software.

In process 401, it is determined whether it is the timing to calculate phase error data, that is, whether the drum motor 1 has made one rotation. If it is not the timing, process 402. Processing 4
03 is skipped and the process moves to process 404. At the time of calculating phase control data, in process 402,
The upper b bits of the phase control data PD obtained from the phase control signal generating means 5 are taken out and stored in the memory C8, and further P
The lower C bits of D are taken out and stored in memory LP. In process 403, the value in memory C3 is multiplied by 2=2-c and stored in memory C5. Here, processing equivalent to a multiplier is performed, but this processing is not performed on the zero-digit component. In other words, by not performing multiplication, the zero-digit component is isometrically doubled by 1/2 ( 16 times), and this is used as the correction value (LP). In process 404, a branch is made depending on the value of LP, and if LP is larger than °1', in process 405, the sum of the memory C5O value plus correction data 1' and KIXVD is stored in memory L.
G, and the process moves to process 407. If it is smaller than LP months, in process 406, the value of memory C5 and KIX
The sum with VD is stored in the memo IJLG, and the process moves to process 407. In other words, the correction data "0°" was added. In process 407, "1" is subtracted from the value in the memory LP.

In process 408, the memory C5O value is sent to the D/A converter 9. This series of processing is executed every time a signal from a signal source or an FC signal arrives at the terminal 13.

Therefore, the correction value is converted into a time-series signal, and the time average during one rotation of the drum motor 1 is made equal to the value of the digit loss component.

For example, the speed control data VD and the phase control data PD are each 8 bits, the number of input nodes of the D/A converter is 9, and K
1=1. If 2 = 24, a 4-bit loss occurs in the conventional phase control device, but if the present invention is used, the number of pulses PN generated by the signal source or FG during one rotation of the drum motor 1 can be reduced. By setting the number to 16 (-2'),
The dividing means 11 shown in FIG. Correction means 12. Value conversion means 14. By using the signal conversion means 15, there is no loss of digits in the phase control data during one rotation of the drum motor 1.

As described above, according to the digital phase control device for a rotating body according to the present embodiment, by using the dividing means, the correction means 2 dividing means, and the signal converting means in the phase control system, the loss component of the phase control data can be adjusted over time. It converts into a time series signal whose average is equal to the lost-digit component, and easily and accurately corrects the lost-digit data caused by limitations such as the number of input focus points of the D/A converter and the number of input points of the adder. can.

Furthermore, in the method shown in the embodiment of the present invention, the correction data converted into a PWM wave changes only once from "1°" to "0" during one rotation of the drum motor 1. By performing this change multiple times, it is possible to better correct the under-digit component during D/A conversion.

Moreover, even when the relationship PN=2c does not hold, PN>
Using a PN that satisfies 2°, convert the zero-digit data into a time-series signal within a predetermined time whose time average is equal to the zero-digit data so that the time average within the predetermined time is equal to the value of the phase control data. is easy. Furthermore, when PN<2', it is difficult to convert all bits of the zero-digit data into a time-series signal within a predetermined time;
If so, it is possible to use the present invention to convert the top two bits of the missing data into a time-series signal within a predetermined time whose time average is equal to the top two bits of the missing data.

Further, the multiplier 61 and the multiplier 7 can be included in the speed control signal generation means 41 and the phase control signal generation means 5, respectively, and the present invention can be easily applied to this case as well.

Note that the present invention is not limited to the above embodiments (
Various modifications are possible based on the gist of the present invention, and these are not excluded from the present invention.

Effects of the Invention As described above, the present invention provides a rotational phase detection means for detecting a rotational phase from a signal corresponding to the rotational phase of a rotating body, and a phase control method for processing an output signal of the rotational phase detection means to obtain a phase control signal. A signal generating means, a dividing means for dividing a phase control signal into an effective component and a lost-digit component of a predetermined number of bits, a correcting means for generating a correction value from the lost-digit component, and a rotational speed detection means for a signal source or a rotating body. a value conversion means for converting the correction value into a time-series signal within a predetermined time using the signal conversion means; The output of the adding means is used to control the phase of the rotary body, so that the data with a loss of precision generated in the digital phase processing system can be processed within the time of one rotation of the rotary body. By converting to a time series signal, it is possible to output a value whose average value within the time of one rotation is approximately equal to data without bit i, and the phase of the rotating body can be output without deteriorating the control accuracy of the phase control system. control can be realized. Therefore, it is possible to obtain excellent control performance such as being able to reduce wow and flutter, and the effect is significant.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a block diagram showing a dividing means, correction means and 2 dividing means in an embodiment of the invention, and Fig. 3 is an explanatory diagram of a data conversion method. , FIG. 4 is a flowchart showing the operation of another embodiment of the present invention, and FIG. 5 is a flowchart showing the operation of another embodiment of the present invention. It is a block diagram of the 11s position. ■... Drum motor, 2... Rotation speed detector, 3... Frequency dividing circuit, 5... Phase control signal generation means, 7... ...multiplier, 11...
...Dividing means, 12...Correction means, 13...
...Signal source or FC signal input terminal, 14...
... Value conversion means, 15 ... Signal conversion means, 16
...Addition means. Name of agent: Patent attorney Shigetaka Awano Figure, l, l 2C12ri 1, 1, 122: 2'
: Figure 20

Claims (2)

[Claims] (1) a signal source, a rotational phase detection means for detecting a rotational phase from a signal corresponding to a rotational phase of a rotating body, and a phase control signal generation means for obtaining a phase control signal based on an output signal of the rotational phase detection means; dividing means for dividing the phase control signal into an effective component and a lost-digit component having a predetermined number of bits; a correcting means for calculating a correction value from the lost-digit component; a value conversion means for converting the time series signal into a time series signal; a signal conversion means for converting the time series signal into a signal whose time average is approximately equal to the loss component; and an addition for adding the output of the signal conversion means and the effective component. A digital phase control device for a rotating body, comprising: means for controlling the phase of the rotating body using the output of the adding means. (2) A digital device for a rotating body according to claim (1), further comprising a rotational speed detection means for generating a signal corresponding to the rotational speed of the rotating body, and using the output of the rotational speed detection means as a signal source. Phase control device.