JPH0457795U

JPH0457795U -

Info

Publication number: JPH0457795U
Application number: JP10007790U
Authority: JP
Priority date: 1990-09-25
Filing date: 1990-09-25
Publication date: 1992-05-18

Description

[Brief explanation of drawings]

第１図は本考案の一実施例を示すブロツク構成
図、第２図は本実施例をマイクロコンピユータに
より構成した場合の基本ブロツク構成図、第３図
は本考案の制御動作を説明するためのフローチヤ
ート、第４図は従来例を説明するためのブロツク
図である。１……内部時計手段、２……時計構成手段、３
……外部時計入力手段、４……差分計算手段、５
……内部時計出力手段、１１……入力ポート、１
２……メモリ、１３……ＣＰＵ、１４……時計機
構、１５……出力ポート。 Fig. 1 is a block configuration diagram showing an embodiment of the present invention, Fig. 2 is a basic block configuration diagram when this embodiment is configured by a microcomputer, and Fig. 3 is a block diagram for explaining the control operation of the present invention. Flowchart FIG. 4 is a block diagram for explaining a conventional example. 1... Internal clock means, 2... Clock configuration means, 3
...External clock input means, 4...Difference calculation means, 5
... Internal clock output means, 11 ... Input port, 1
2...Memory, 13...CPU, 14...Clock mechanism, 15...Output port.

Claims

[Scope of Claim for Utility Model Registration] (1) In a clock device that outputs time synchronized with external clock information input from the outside, external clock input means for inputting external time information, and internal clock means for generating internal time. and a differential clock means for calculating the time difference between the internal clock and the external clock and requesting the later-described clock calibration means to calibrate the clock when the difference exceeds a certain value, a clock calibration means for calibrating the internal clock, and an internal clock. A clock device comprising: an internal clock output means for outputting information; (2) Claim (1) further characterized in that the difference calculation means is configured by a microcomputer.
The clock device described in .