JPH0457940U - - Google Patents
Info
- Publication number
- JPH0457940U JPH0457940U JP9936090U JP9936090U JPH0457940U JP H0457940 U JPH0457940 U JP H0457940U JP 9936090 U JP9936090 U JP 9936090U JP 9936090 U JP9936090 U JP 9936090U JP H0457940 U JPH0457940 U JP H0457940U
- Authority
- JP
- Japan
- Prior art keywords
- pulse signal
- frame pulse
- main frame
- signal
- digital signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000001360 synchronised effect Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Time-Division Multiplex Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Description
第１図は、本考案実施例の構成を示すブロツク
図。第２図は、従来例の構成を示すブロツク図。
１……スタツフイング回路、２……フレームカ
ウンタ回路、３……比較回路、４……可変遅延回
路、５……メモリ回路、６……制御手段、７……
スタツフイング手段。
FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional example. DESCRIPTION OF SYMBOLS 1...Stuffing circuit, 2...Frame counter circuit, 3...Comparison circuit, 4...Variable delay circuit, 5...Memory circuit, 6...Control means, 7...
Statfing means.
Claims (1)
トレートとを変更し、与えられる主フレームパル
ス信号に同期する新たなデイジタル信号を生成す
るスタツフイング手段を備えたデイジタル信号同
期装置において、 与えられる主フレームパルス信号と上記スタツ
フイング手段が出力するフレームパルス信号との
位相差に応じてこの主フレームパルス信号を遅延
させた新たな主フレームパルス信号を生成し、上
記スタツフイング手段に与える制御手段 を備えたことを特徴とするデジタル信号同期装置
。 ２ 上記制御手段は、上記スタツフイング手段に
与えられる主フレームパルス信号と上記スタツフ
イング手段が出力するフレームパルス信号との位
相差を検出してこの位相差に相応の制御信号を生
成する比較回路およびこの制御信号に基づきこの
主フレームパルス信号に与える遅延量を変更して
新たな主フレームパルス信号を生成し、上記スタ
ツフイング手段に与える可変遅延回路を備えた請
求項１記載のデイジタル信号同期装置。[Claims for Utility Model Registration] 1. In a digital signal synchronizer equipped with stuffing means for changing the frame structure and bit rate of an incoming digital signal and generating a new digital signal synchronized with a given main frame pulse signal. , generates a new main frame pulse signal by delaying the main frame pulse signal according to the phase difference between the given main frame pulse signal and the frame pulse signal outputted by the stuffing means, and supplies it to the stuffing means. A digital signal synchronization device characterized by comprising a control means. 2. The control means includes a comparison circuit that detects a phase difference between the main frame pulse signal applied to the stuffing means and a frame pulse signal outputted from the stuffing means and generates a control signal corresponding to this phase difference; 2. The digital signal synchronization device according to claim 1, further comprising a variable delay circuit for generating a new main frame pulse signal by changing the amount of delay given to the main frame pulse signal based on the control signal and supplying the new main frame pulse signal to the stuffing means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9936090U JPH0457940U (en) | 1990-09-21 | 1990-09-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9936090U JPH0457940U (en) | 1990-09-21 | 1990-09-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0457940U true JPH0457940U (en) | 1992-05-19 |
Family
ID=31841227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9936090U Pending JPH0457940U (en) | 1990-09-21 | 1990-09-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0457940U (en) |
-
1990
- 1990-09-21 JP JP9936090U patent/JPH0457940U/ja active Pending
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