JPH045817A - Epitaxial growth layer; its growth method; manufacture of semiconductor device and high-resistance region - Google Patents

Abstract

PURPOSE:To realize a high-carrier density in mixed crystals of a plurality of semiconductors by a method wherein the semiconductor mixed crystals are replaced with a superlattice structure whose forbidden band width is equivalent or similar. CONSTITUTION:The temperature of an Fe-doped semiinsulating (100) InP substrate 1 is raised; an undoped In0.5sAl0.5sAs layer is grown in 2000Angstrom as a high- resistance buffer layer 2; after that, a C-doped GaAs layer 4 (concentration of C: 1X10<21>cm<-3>) is grown as an 8-molecule layer. In succession, undoped GaAs as a 0.7-molecule layer, an undoped InAs layer as a 10.6-molecule layer and an undoped GaAs layer as a 0.7-molecule layer are grown sequentially; only a monomolecular layer on the GaAs layer 4 becomes an undoped In0.3Ga0.7 As layer 5; a succeeding 10-molecule layer becomes an undoped InAs layer; a next monomolecular layer becomes an undoped In0.3Ga0.7As layer 5. A laminated structure by layers 4, 5, 6, 5 is used as one cycle; 10 cycles are grown. Thereby, a superlattice layer 3 is realized.

Description

[Detailed description of the invention]

FIELD OF INDUSTRIAL APPLICATION The present invention relates to an epitaxially grown layer of a semiconductor material having a high carrier density layer, a method for growing the same, a semiconductor device having such an epitaxially grown layer, and a method for manufacturing a high resistance region.

[Prior Art 1] Amphoteric impurities, which behave as either p-type or n-type depending on the type of semiconductor material, are somewhat inconvenient to handle, but are often used in cases where they have many advantages. For example, C, which is a group IV element, is an amphoteric impurity in an nr-v group compound semiconductor, but behaves as an n-type impurity in GaAs. GaA
Compared to Be, Mg, Zn, etc., which are n-type impurities for s, C has a smaller diffusion coefficient and can achieve a high carrier density of about 102102l'. Methods for manufacturing semiconductor devices have been developed. Such an example can be found in Applied Physics Letters 54 (19
1989) pages 39 to 41 (Applied Ph
ysics Letters 54 (1989) PP
39-41). (Problems to be Solved by the Invention) The above conventional technology does not take into account the use of the impurities in the mixed crystal of compound semiconductors, and because different types of charges coexist in the carriers created by the impurities and cancel each other out, There was a problem that it was difficult to increase the carrier density.For example, C is an n-type impurity in GaAs, but in
Since s is an n-type impurity, its mixed crystal InxGa1-
In the composition of xAs with 0.2<x<0.8, it was impossible to achieve high carrier density with any conductivity type. A first object of the present invention is to provide an epitaxially grown layer of a semiconductor material that achieves a high carrier density in a mixed crystal of a first semiconductor and a second semiconductor. A second object of the present invention is to provide an epitaxial growth method for manufacturing the above-mentioned epitaxial growth layer. A third object of the present invention is to provide a semiconductor device using the above epitaxial growth layer. A fourth object of the present invention is to provide a method for manufacturing a high-resistance region in which the epitaxial growth layer is the high-resistance region. [Means for Solving the Problems] The first object is to (1) provide an epitaxial growth layer having a superlattice structure consisting of at least a first semiconductor and a second semiconductor; Either one of the semiconductors has an impurity that exhibits a first conductivity type in the first semiconductor and a second conductivity type different from the first conductivity type in the second semiconductor. (2) In the epitaxial growth layer described in 1 above, the epitaxial growth layer is characterized in that the semiconductor [1st] and the second semiconductor are m-v group compound semiconductors, and the impurity is a group IV element. layer, (3)
In the epitaxial growth layer described in 2 above, the first
(4-) In the epitaxial growth layer described in 1.2 or 3 above, the superlattice structure is , an epitaxially grown layer characterized in that its period is equal to or less than a critical film thickness at which dislocations occur at the interface of each semiconductor layer constituting the epitaxially grown layer, (5) the epitaxially grown layer described in 1.2.3 or 4 above, (6) any of the above 1 to 5, wherein the other semiconductor different from one semiconductor has another impurity having the same conductivity type as that in the semiconductor to which the impurity is added; In the epitaxial growth layer according to the above, the superlattice structure is composed of a one-to-one composition of a first semiconductor and a second semiconductor, and is formed by repeating one molecular layer of the first semiconductor and one molecular layer of the second semiconductor. This is achieved by an epitaxially grown layer characterized in that it is composed of: The second purpose is to (7) repeat the steps of epitaxially growing a first semiconductor of a desired molecular layer and epitaxially growing a second semiconductor of a desired molecular layer on a compound semiconductor substrate to form a superlattice. In the epitaxial growth method for forming a structure, in any one of the above steps, a first conductivity type is formed in the first semiconductor.
an epitaxial growth method characterized in that the epitaxial growth layer is doped with an impurity exhibiting a second conductivity type different from the first conductivity type in the semiconductor; (8) in the epitaxial growth method described in 7 above, the first semiconductor and Second
an epitaxial growth method characterized in that the semiconductor is an m-v group compound semiconductor and the impurity is a TV group element; (9) the epitaxial growth method described in 7 or 8 above, which is different from either one of the steps above; In the process of
Another impurity having the same conductivity type as that in the semiconductor to which the above impurities are added is added to the epitaxially grown layer by 1.-
This is achieved by an epitaxial growth method characterized by The third object is to (10) provide a semiconductor device having a bipolar transistor on a compound semiconductor substrate, wherein the epitaxial growth layer according to any one of [6] to [6] above is provided on the compound semiconductor substrate; (11) A semiconductor device having a field effect transistor on a compound semiconductor substrate, wherein the compound semiconductor substrate is provided with a semiconductor device according to any one of 1 to 6 above on the compound semiconductor substrate. By providing an epitaxial growth layer, the above electric field effect 1
- The channel layer of the transistor is achieved by a semiconductor device characterized in that it is provided in the epitaxially grown layer. The fourth object is characterized in that (12) a superlattice structure is formed by the epitaxial growth method described in 7.8 or 9 above, and a desired portion of the superlattice structure is disordered to form a high resistance region. (13) A method for manufacturing a high resistance region as described in 12 above, wherein the disordering is performed by selective diffusion of impurities, (14) In the method for manufacturing a high-resistance region as described in 12 above, the disordering is performed by selectively implanting ions into the superlattice structure through a mask with a desired pattern, followed by heat treatment. Manufacturing method (15) In the method for manufacturing a high resistance region as described in 12 above, the disordering is performed by forming a desired pattern of an insulating film on the superlattice structure and then heat-treating the disordered structure. This is achieved by a method of manufacturing a resistive region. In the epitaxially grown layer of the present invention, by adopting the configuration described in item (4) above, it is possible to obtain an epitaxially grown layer of a semiconductor material in which the crystallinity of the mixed crystal is maintained at high quality. Further, by employing the configuration described in item (6) above, it is possible to obtain an epitaxially grown layer of a semiconductor material with good reproducibility. [Operation] By replacing the semiconductor mixed crystal with a superlattice structure having an equivalent or similar forbidden band width, it becomes possible to add impurities to any layer of the constituent semiconductor. As a result, an arbitrary conductivity type can be realized while maintaining properties equivalent to high carrier density and small diffusion coefficient possessed by the impurity. At this time, due to the presence of the layer in which the impurity is not added, the overall carrier density is lower than in the layer in which the impurity is added, but since there is no carrier compensation effect, it is lower than when the impurity is uniformly added to the mixed crystal. You can make it bigger. This effect is particularly noticeable in a region where the mixed crystal composition X is close to 0.5. If it is desired to further increase the carrier density, another impurity exhibiting a desired conductivity type may be added to the layer to which the impurity is not added. Furthermore, by setting the period of the superlattice to be less than or equal to the critical film thickness for dislocation generation, it becomes possible to maintain high-quality crystallinity that can be applied to high-performance semiconductor devices. Furthermore, when the composition X of the mixed crystal is 0.5, by configuring the superlattice with one atomic (or molecule) layer of each semiconductor, carrier mobility reduction due to alloy scattering is suppressed,
Moreover, it becomes possible to perform epitaxial growth with good reproducibility. Further, when the superlattice structure is selectively disordered, the superlattice becomes a mixed crystal due to the disordering, so that a high resistance region is selectively formed as a result of the compensation effect due to the generation of carriers of different conductivity types. This effect becomes more pronounced as the mixed crystal composition approaches 0.5, and can contribute to higher performance of semiconductor devices. [Example] Example 1 Hereinafter, highly doped p-type InO,S which is an example of the present invention
3 The molecular beam epitaxial growth method of Ga0.47A'' layer will be explained with reference to FIG.
After etching with % bromine methanol solution and cleaning, it is mounted in a 10 holder and placed in a molecular beam epitaxial growth layer. The temperature of the substrate is raised under As molecular beam irradiation, the oxide film is removed, and the temperature is raised to 450° C., which is the growth temperature. Growth rate is 0.
The speed was approximately 1 μm/h. As shown in FIG. 1(a), undoped In, 52A is used as the high resistance buffer layer 2.
After growing 2000 layers of no, 411ASJ11, about 600 layers of superlattice M3 corresponding to highly doped p-type Ino, 3Gao, 47As layers are formed as follows. As shown in Fig. 1(b), first, 8 molecular layers of C-doped GaAs layer 4 (C concentration: lXl0''-3) are grown.C doping is carried out by heating a graphite filament to about 2000'C by passing an electric current through it. Subsequently, 0.7 molecular layer of undoped GaAs and 0.7 molecular layer of undoped InAsM were added.
By growing 10.6 molecular layers of undoped GaAsJl and 0.7 molecular layers of undoped GaAsJl, only one molecular layer on the C-doped GaAs layer 4 becomes undoped Ino, 3Ga[l
, 7As layer 5, and the next <10 molecular layers are undoped In
The As layer 6 and the next one molecular layer are undoped In. ,,Ga0
, 7AS layer 5. In reality, it is thought that there are irregularities of about one molecular layer at the interface of each layer, but the superlattice layer 3 is highly doped p-type In. There were no practical problems in obtaining the ,53Ga0.47AS layer. C-doped GaAs layer4. Undoped Ino,
, Ga, , AsJi15, undoped In
By growing 10 periods with the layered structure of As layer 6, undoped Ino, 3Gao, and 7As layer 5 as one period (however, the top layer has undoped Ino3Gao, 7As layer 5).
(no s-layer 5), a superlattice layer 3 was realized. As a result of hole measurement, the hole density in superlattice M3 is 3
10"cm-3. This is GaAs and InAs
In both cases, Be, which becomes a P-type impurity, is Ino, 53Ga
This exceeds the upper limit of the hole density obtained by uniform doping in o4□As, I x 10"cm-3, and this method is excellent for realizing highly doped p-type Ino, 5iGao, and 47As layers. According to this example, a high carrier density was achieved by suppressing the carrier compensation effect in the mixed crystal while taking advantage of the small diffusion coefficient of C and the possibility of high doping. In the example, the thicknesses of the C-doped GaAs layer 4 and the undoped InA+Jf!6 were 8 and 10 molecular layers, respectively, but any thickness may be used as long as it does not cause dislocations at the interface.However, Ino, 53Gao, 4. In order to approximate the As mixed crystal, it is desirable that the period of the superlattice be short. Also, the C-doped GaAs layer 4 and the undoped InAs
The order in which the layers 6 are formed may be reversed. If you want to further increase carrier density, undoped InA
A p-type impurity such as Be may be added to the s-layer 6. In this embodiment, InP is lattice-matched to the InP substrate 1. , 53
Although Gao and 4□As epitaxial growth methods were shown,
Of course, this method can also be applied to mixed crystals of other compositions. Example 2 Hereinafter, highly doped p-type ■no, g which is an example of the present invention
The molecular layer epitaxial growth method of A11o, 25Gao, and 2gAs layers will be explained with reference to FIG. 0.05 Fe-doped semi-insulating (100) InP substrate 1
After etching with a % bromine methanol solution, the sample was placed in an organometallic vapor phase epitaxial growth apparatus. Arsine (A
After removing the surface oxide film of the InP substrate 1 by heating while supplying st(3), the growth temperature is 450
'Set to C. Started supplying triethyl indium, triethyl aluminum, and triethyl gallium, undoped Ino, 5Afi 0.2Sca0.2! ;”s
Grow layer 7 by 2000 people. Growth rate is 0.1μm/h
(Figure 2(a)). Highly doped n-type Ino, sA Q o, zsGaa, zs
The superlattice layer 3, which corresponds to the As layer, has approximately 200 layers as shown in Figure 2 (b
) was realized by the superlattice structure. That is, when growing one molecule layer of C-doped A Qo, s Gao, 6 AsM9, triethylaluminum and trimethylgallium were each flowed in an amount equivalent to 0.5 atomic layer, followed by 1 atomic layer of arsine.
Flow equivalent to an atomic layer. Here, trimethyl gallium is used as a source of C doping as well as a source of Ga. When growing a single molecular layer of undoped InAs layer 10,
After triethyl indium is flowed in an amount equivalent to one atomic layer, arsine is flowed in an amount equivalent to one atomic layer. In this way, a superlattice consisting of one molecular layer of C-doped A U o, 1Gao, 5AsN9 and one molecular layer of undoped InAs layer 10 was fabricated by metalorganic vapor phase epitaxial growth. As a result of hole measurement, the hole density in layer 3 is 4X1020c
m-3 and In11. EAQD, 7. l;GaO,
2! ; Hole concentration 1 when C is uniformly added to As mixed crystal
015cm-3, the hole density could be dramatically increased, and a value exceeding the upper limit value I x 102102O'' when Be was used as the p-type impurity could be achieved.This Example According to , it is possible to achieve a high carrier density while taking advantage of the small diffusion coefficient of C and the possibility of high doping, and because the doping is controlled for each molecular layer, high carrier density can be achieved with good reproducibility. In this example, an example of highly doped p-type InD, .
In the o,xGaO,4As layer, C-doped Au o,,Ga
o, As layer 9 is C-doped A n . ,2Gao,,A
In the case of Ino, s Gao, and 5As layers, the C-doped A Q o, , Gao, and As layer 9 may be replaced with a C-doped GaAs 1-molecular layer. Especially Ina
, 5Gao, and 5As layers, forming a superlattice for each molecular layer has the effect of reducing alloy scattering and improving carrier mobility. Also, highly doped n-type In+1. GA”0
．． To realize a 2GGa11.25As layer by C doping, replace the C-doped A Q oSGao, , As layer 9 with an undoped A Q ,5Gao,, As1 monolayer, and replace the undoped InAs layer 10 with a C-doped InAs monolayer. good. Example 3 Hereinafter, InA Q As layer I which is an example of the present invention
A method for manufacturing an nGaAs-based heterojunction bipolar transistor will be explained with reference to FIG. A Fe-doped semi-M-type (100) InP substrate 1 was placed in a molecular beam epitaxial growth apparatus, and Example 1. As shown in FIG. 3(a), as shown in FIG.
Grow the layer by 2000 people. Next is highly doped n-type In. 5
3Gao, 47As layer 11 (Si concentration: 5X 1018
cm-3) for 5000 people, n-type doped In. ,,3Ga
o, 4, As layer 12 (Si concentration: 5×10101G”)
to grow by 4,000 people. Next is highly doped n-type InQ! ,
:1 The superlattice N3 corresponding to the Ga0.47As layer is formed with the same structure as in Example 1, and n-type doped In is formed on it. 52
AQ0.411AS layer 13 (Sill X 10110
2000 people, highly doped n-type InO, S: 1G
ao, 47As layer 14 (Si: sxlolgcm-”
) to grow by 2000 people. As shown in FIG. 3(b), the surface of the superlattice layer 3 is etched with highly doped n-type Ino by photolithography and etching.
5aGao, 47The surface of the AS layer 11 and the middle of the high-resistance buffer layer 2 are exposed, C+ ions are implanted into the region 15 corresponding to the outer part of the external base, and the temperature is 10°C at 800°C.
Heat treated for minutes. As a result, the superlattice structure of region 15 became disordered and became a mixed crystal, and due to the compensation effect due to the generation of heterogeneous charge-bearing carriers, it changed to a high resistance region with an electron density of about 1015 cm''-3. ), the n-type doped Ino,=,Gao,,7As layer 12 under the external base region is
``Ion implantation was performed to form a high resistance region 16. Regions 15 and 16 are for reducing the parasitic capacitance between the base and collector.Finally, the emitter electrode 17, the base electrode 18, and the collector electrode 19. According to this example, InO with a high hole density of 3X 10"cm-3, which could not be obtained by uniformly adding Be or C, was formed.
! Since the 13 Gao and 4 VAs layers can be realized, the base resistance can be lowered, which has the effect of improving the operating speed of the Peter junction bipolar 1 helangister. Also. Of the external base region, it only contributes to the formation of the base electrode,
Conventional H+ or 0+ ion implantation was not sufficient to increase the resistance of regions 15 that are unnecessary for the operation of a semiconductor device, but by making the superlattice disordered as in this embodiment, Since the parasitic capacitance between the base and the collector can be further reduced, there is also the effect of further increasing the operating speed of the semiconductor device. Embodiment 4 Hereinafter, a method for manufacturing a P-channel hetero insulated gate field effect transistor, which is an embodiment of the present invention, will be explained with reference to FIG. The semi-insulating GaAs substrate 20 is placed in an organometallic vapor phase epitaxial growth apparatus, heated in an arsine atmosphere, the surface oxide film is removed, and then the temperature is lowered to 450°C. As shown in FIG. 4(a), after growing 2000 undoped GaAs layers 21, highly doped n-type In[+, 5 Gao, S As
About 50 superlattice layers 3 corresponding to 1 fl are grown. The superlattice M3 was grown by a molecular layer epitaxial growth method in which the feedstock was alternately switched. Specifically, Example 2
The superlattice layer 3 is a highly doped p-type Ino, Gao, 5As layer, and the C-doped A[, 5Ga,..., AJ9 is C
Growth was performed by replacing the doped GaAs monomolecular layer. The hole density in the superlattice layer 3 is the same as in Example 2, 4
It was 10"cm7". Subsequently, by the usual organometallic vapor phase epitaxial growth method in which raw materials are continuously supplied,
2000 layers of undoped AQ,,3Ga,,7AsJi 23, highly doped n-type GaAs layer 24 (Si:5X
10"c+n-') was grown for 2000 layers. The sample was taken out from the growth apparatus, a 5in2 film 25 (1000 layers) was deposited as shown in FIG. Only the 5in2 film 25 is left in the area.When heat treatment is performed at 800'C for 2 minutes in this state, the vacancies of group ■ atoms are supplied by the 5in2 film 25, so that only the 5 film islands of the SiO□ film 25 form a superlattice layer. The superlattice in 3 is disordered, and the resistance of the region 26 is increased.Next, as shown in FIG. and
Performs isolation of elements. Subsequently, by selective dry etching, only the highly doped n-type GaAs layer 24 in the gate region is etched to form undoped A Q , , Ga,
The surface of the 7As layer 23 is exposed. Finally, a gate electrode 28, a source electrode 29, and a drain electrode 30 were formed to produce a p-channel hetero insulated gate field effect transistor (FIG. 4(d)). According to this embodiment, the carrier density of the superlattice layer 3 serving as a channel layer can be made much higher than that of the conventional method, so that there is an effect that the performance of the semiconductor device can be improved. In addition, it was difficult to increase the resistance of the InGaAs channel layer in the element isolation region by implanting only O+ ions, but as in this example,
The combined use of selective disordering of the superlattice using a 5in2 film also has the effect of perfecting element insulation isolation. In this example, the superlattice layer 3 is made of In, 5Ga, .
Although As is used, it is of course possible to create other mixed crystal compositions by combining the method of Example 1.

【Effect of the invention】

Since the present invention is configured as described above, it produces the effects described below. By replacing the compound semiconductor mixed crystal with a superlattice having an equivalent or similar forbidden band width, impurities can be added to any layer of the constituent semiconductor. As a result, an arbitrary conductivity type can be realized while maintaining the properties equivalent to the high carrier density and small diffusion coefficient possessed by the impurity. Furthermore, by adding another impurity exhibiting a desired conductivity type to the layer to which the impurity is not added, even higher carrier density can be achieved. Furthermore, by setting the period of the superlattice to be less than or equal to the critical film thickness for dislocation generation, a high quality semiconductor layer can be realized. Furthermore, when the composition of the mixed crystal is 0.5, by configuring the superlattice with one atomic (or molecule) layer of each semiconductor, carrier mobility reduction due to alloy scattering is suppressed,
Moreover, epitaxial growth can be performed with good reproducibility. Furthermore, by selectively disordering the superlattice structure, a high resistance region can be easily and selectively obtained.

[Brief explanation of drawings]

FIG. 1 shows a highly doped n-type Inn, 53, according to an embodiment of the present invention.
Gan, +7ASJ! FIG. 2 is a vertical cross-sectional view of a grown layer showing the steps of molecular beam epitaxial growth of a superlattice layer corresponding to f, and FIG. 2 is a highly doped n-type Ino, A
FIG. 3 is a vertical cross-sectional view of a grown layer showing the steps of a metal organic vapor phase epitaxial growth method of a superlattice layer corresponding to Qo, zsGao, and zsAs layers, and FIG. 3 shows a method for manufacturing a heterojunction bipolar transistor according to an embodiment of the present invention. FIG. 4 is a vertical cross-sectional view of a device showing a method of manufacturing a hetero insulated gate field effect transistor according to another embodiment of the present invention. 1...InP substrate 2...High resistance buffer layer 3...Superlattice layer 4...C-doped GaAs
J15... Undoped In, 3Ga, 7As layer 6
...Undoped InAs layer 7...Undoped Ino, , Afl O, 25Ga[
+, 7.5As layer 9...C doped A Q n, 5Gap
,, AsjiIO...Undoped InAs, 1F 11-...Highly doped n-type In. , 5aGa8.47AS
Layer 12 - n-type doped ■nQ,,3GaI]41As layer 1
3-n-type doped In[1,5ZAQ0.411AS layer 1
4-...Highly doped n-type 110.53G80.47AS layer 15.16.26...Region 17...Emitter electrode 18...Base electrode 19...Collector electrode 2O-GaAs substrate 21...Undoped GaAs layer 23--undoped A Q o, , Ga
o, As layer 24...highly doped n-type GaAs layer

Claims (1)

[Claims] 1. In an epitaxial growth layer having a superlattice structure consisting of at least a first semiconductor and a second semiconductor, either the first semiconductor or the second semiconductor is 1. An epitaxial growth layer comprising an impurity that exhibits a first conductivity type in a first semiconductor and a second conductivity type different from the first conductivity type in a second semiconductor. 2. The epitaxial growth layer according to claim 1, wherein the first semiconductor and the second semiconductor are group III-V compound semiconductors, and the impurity is a group IV element. 3. The epitaxial growth layer according to claim 2, wherein the first semiconductor is GaAs and the second semiconductor is InA.
s, and the impurity is C. 4. The epitaxial growth layer according to claim 1, 2 or 3, wherein the period of the superlattice structure is equal to or less than a critical film thickness at which dislocations occur at the interface of each semiconductor layer constituting the superlattice structure. layer. 5. In the epitaxial growth layer according to claim 1, 2, 3 or 4, the other semiconductor different from the one semiconductor contains another impurity having the same conductivity type as that in the impurity-doped semiconductor. An epitaxial growth layer comprising: 6. The epitaxial growth layer according to any one of claims 1 to 5, wherein the superlattice structure has a one-to-one composition of a first semiconductor and a second semiconductor, and one molecular layer of the first semiconductor and one molecular layer of the second semiconductor. 1. An epitaxial growth layer characterized in that it is constituted by repeating a single molecular layer of a semiconductor. 7. In an epitaxial growth method in which a superlattice structure is formed by repeating the steps of epitaxially growing a first semiconductor of a desired molecular layer and epitaxially growing a second semiconductor of a desired molecular layer on a compound semiconductor substrate, In one of the above steps, the epitaxial growth layer is doped with an impurity exhibiting a first conductivity type in the first semiconductor and a second conductivity type different from the first conductivity type in the second semiconductor. An epitaxial growth method characterized by: 8. The epitaxial growth method according to claim 7, wherein the first semiconductor and the second semiconductor are group III-V compound semiconductors, and the impurity is a group IV element. 9. The epitaxial growth method according to claim 7 or 8, in which another impurity having the same conductivity type as that in the semiconductor to which the impurity is added is added to the epitaxial growth layer in another step different from either one of the steps. An epitaxial growth method characterized by doping. 10. A semiconductor device having a bipolar transistor on a compound semiconductor substrate, wherein the epitaxial growth layer according to any one of claims 1 to 6 is provided on the compound semiconductor substrate, and the base of the bipolar transistor is
A semiconductor device characterized by being provided in the epitaxial growth layer. 11. In a semiconductor device having a field effect transistor on a compound semiconductor substrate, on the compound semiconductor substrate,
The epitaxial growth layer according to any one of claims 1 to 6 is provided, and the channel layer of the field effect transistor is
A semiconductor device characterized by being provided in the epitaxial growth layer. 12. A method for manufacturing a high resistance region, comprising forming a superlattice structure by the epitaxial growth method according to claim 7, 8 or 9, and disordering a desired portion of the superlattice structure to form a high resistance region. . 13. The method of manufacturing a high resistance region according to claim 12, wherein the disordering is performed by selectively diffusing impurities. 14. The method of manufacturing a high resistance region according to claim 12, wherein the disordering is performed by selectively implanting ions into the superlattice structure through a mask with a desired pattern, and then heat-treating the superlattice structure. Method of manufacturing a resistive region. 15. The method of manufacturing a high resistance region according to claim 12, wherein the disordering is performed by forming a desired pattern of an insulating film on the superlattice structure and then heat-treating the structure. Production method.