JPH045841A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH045841A
JPH045841A JP2107160A JP10716090A JPH045841A JP H045841 A JPH045841 A JP H045841A JP 2107160 A JP2107160 A JP 2107160A JP 10716090 A JP10716090 A JP 10716090A JP H045841 A JPH045841 A JP H045841A
Authority
JP
Japan
Prior art keywords
layer
lsi
chip
metal
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2107160A
Other languages
Japanese (ja)
Other versions
JP2533810B2 (en
Inventor
Toshio Watabe
利男 渡部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP2107160A priority Critical patent/JP2533810B2/en
Publication of JPH045841A publication Critical patent/JPH045841A/en
Application granted granted Critical
Publication of JP2533810B2 publication Critical patent/JP2533810B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To commonly use mounting LSI and a chip direct mounting LSI by providing a plurality of electrodes of a first metal wiring layer, a second metal layer and a third metal interconnection layer on the second metal layer. CONSTITUTION:A second metal layer 12 is so formed as to cover substantially entire circuit of an LSI chip 10. The layer 12 is maintained at a predetermined potential. A third metal interconnection layer is formed in the layer 12. The third layer is mainly formed of a metal interconnection pattern 13 and a connecting electrode pad 14. The pad 14 is a chip direct mounting connecting electrode, and the pads 14 are electrically connected to the connecting electrode pad 11 of the first layer. Thus, since the pad 11 is wired to the pad 14 by the pattern 3, the normal mounting LSI and the chip direct mounting LSI can be commonly used.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、チップダイレクト実装を行う半導体装置に関
する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device that performs chip direct mounting.

［従来の技術］ ＣＯＧ　（チップオングラス）等のチップダイレクト実
装用のＬＳＩ（大規模集積回路）チップは、チップの周
囲部のみならず内側部にも接続用電極パッドが存在して
いる。このため、ＬＳＩチップを開発する当初からチッ
プダイレクト実装専用として設計する必要があり、他の
通常実装用ＬＳＩ。[Prior Art] LSI (large scale integrated circuit) chips for chip direct mounting such as COG (chip on glass) have connection electrode pads not only on the periphery of the chip but also on the inside. For this reason, from the beginning of LSI chip development, it is necessary to design it exclusively for chip direct mounting, and other LSI chips for normal mounting must be designed.

例えばモールド実装用ＬＳＩ、ＴＡＢ　（テープオトメ
イテドボンディング）実装用ＬＳＩ等をチップダイレク
ト実装用ＬＳＩへ流用することは難しい。また逆に、チ
ップダイレクト実装用ＬＳＩを通常実装用ＬＳＩへ流用
することも困難である。For example, it is difficult to use LSIs for mold mounting, LSIs for TAB (tape automated bonding) mounting, etc. as LSIs for chip direct mounting. Conversely, it is also difficult to use an LSI for chip direct mounting as an LSI for normal mounting.

［発明が解決しようとする課題］ 当初からチップダイレクト実装専用として設計したとし
ても、接続用電極パッドが１層のメタル配線で形成され
ると、チップの内側部にある接続用電極パッドからワイ
ヤボンディング法によって結線を行うことができない。[Problems to be Solved by the Invention] Even if the device is designed from the beginning exclusively for chip direct mounting, if the connection electrode pad is formed of a single layer of metal wiring, wire bonding from the connection electrode pad on the inside of the chip will occur. Wiring cannot be done by law.

このため、チップ内側部の接続用電極パッドに関してそ
のＬＳＩの特性試験を行うことが難しく、通常実装用Ｌ
ＳＩに比して開発期間がどうしても長くなってしまうと
いう問題点があった。For this reason, it is difficult to perform characteristic tests on the LSI with respect to the connection electrode pads inside the chip, and
There was a problem that the development period was inevitably longer than that of SI.

さらに、電源配線の処理、多数の回路に共通に必要な信
号線の処理、接続用電極パッド周辺の規定等により、通
常実装用ＬＳＩに比してチップサイズがどうしても大き
くなってしまうという問題点もあった。Furthermore, there is the problem that the chip size is inevitably larger than that of a normal LSI due to the processing of power supply wiring, the processing of signal lines commonly required for many circuits, and the regulations surrounding the connection electrode pads. there were.

接続用電極パッド等のメタル配線層とチップダイレクト
実装用のメタル配線層との２層構造のメタル配線層を備
えるように構成すれば、上述の問題点が解消できしかも
通常実装用ＬＳＩとチップダイレクト実装用ＬＳＩとを
共用することが可能となる。しかしながら、メタル配線
層間のタロストーク等によって電気的特性の変化が生じ
るため、この種の構成をＬＳＩに実際に適用することは
非常に難しい。The above-mentioned problems can be solved by configuring a metal wiring layer with a two-layer structure consisting of a metal wiring layer for connection electrode pads, etc. and a metal wiring layer for chip direct mounting. It becomes possible to share the mounting LSI. However, it is very difficult to actually apply this type of configuration to LSI because changes in electrical characteristics occur due to talostalk between metal wiring layers.

従って本発明の目的は、通常実装用ＬＳＩを電気的特性
変化を与えることなく共用することが可能なチップダイ
レクト実装による半導体装置を提供することにある。SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor device by chip direct mounting, in which an LSI for normal mounting can be used in common without changing the electrical characteristics.

［課題を解決するための手段］ 上述の目的を達成する本発明の要旨は、半導体チップ上
に設けられた第１メタル配線層の複数の電極と、半導体
チップ上の少なくとも一部に設けられており所定電位に
設定された第２メタル層と、第２メタル層上に設けられ
たチップダイレクト実装用の複数の電極パッドを有して
おりこれら複数の電極パッドと第１メタル配線層の前述
の複数の電極とを接続する第３メタル配線層とを備えた
ことにある。[Means for Solving the Problems] The gist of the present invention for achieving the above-mentioned object is to provide a plurality of electrodes of a first metal wiring layer provided on a semiconductor chip, and a plurality of electrodes provided on at least a portion of the semiconductor chip. It has a second metal layer set to a predetermined potential, and a plurality of electrode pads for chip direct mounting provided on the second metal layer, and these electrode pads and the first metal wiring layer have a second metal layer set to a predetermined potential. The third metal wiring layer is provided to connect the plurality of electrodes.

［作用］ 通常実装用ＬＳＩで構成可能な半導体チップ上に設けら
れた第１メタル配線層の電極が第３メタル配線によりそ
の第３メタル配線層の電極パッドに接続されている。第
３メタル配線層がチップダイレクト実装用として構成さ
れているため、通常実装用ＬＳＩをチップダイレクト実
装することができる。第１メタル配線層と第３メタル配
線層との間に、所定電位に設定された第２メタル層が設
けられているので、第１メタル配線の電気的影響が第３
メタル配線に及ぼされる恐れがない。[Function] The electrodes of the first metal wiring layer provided on the semiconductor chip which can be constituted by an LSI for normal mounting are connected to the electrode pads of the third metal wiring layer by the third metal wiring. Since the third metal wiring layer is configured for chip direct mounting, an LSI for normal mounting can be mounted directly on the chip. Since the second metal layer set to a predetermined potential is provided between the first metal wiring layer and the third metal wiring layer, the electrical influence of the first metal wiring is
There is no risk of damage to metal wiring.

［実施例］ 以下図面を用いて本発明の実施例を詳細に説明する。[Example] Embodiments of the present invention will be described in detail below using the drawings.

第１図は本発明の一実施例としてチップダイレクト実装
した半導体装置の構成を概略的に示す平面図である。FIG. 1 is a plan view schematically showing the structure of a semiconductor device mounted directly on a chip as an embodiment of the present invention.

同図において、１０は例えばモールド実装用、ＴＡＢ実
装用等の通常実装用のＬＳＩチップ、１１はＬＳＩチッ
プ１０上に設けられた第１．メタル配線層の接続用電極
パッドをそれぞれ示している。In the figure, 10 is an LSI chip for normal mounting such as mold mounting or TAB mounting, and 11 is a first LSI chip provided on the LSI chip 10. Each of the connection electrode pads of the metal wiring layer is shown.

ＬＳＩチップ１０の回路部のほぼ全域を覆うように第２
メタル層１２が積層されている。この第２メタル層１２
は、一定の電位、例えば電源電位又はアス電位に維持さ
れている。なお、第２メタル層１２が回路部の必ずしも
全域を覆う必要はない。The second layer covers almost the entire circuit section of the LSI chip 10.
Metal layers 12 are laminated. This second metal layer 12
is maintained at a constant potential, for example, a power supply potential or an earth potential. Note that the second metal layer 12 does not necessarily need to cover the entire circuit section.

第２メタル層１２の上には、第３メタル配線層が積層さ
れている。この第３メタル配線層は、メタル配線パター
ン１３と接続用電極パッド１４とから主として構成され
ている。A third metal wiring layer is laminated on the second metal layer 12. This third metal wiring layer is mainly composed of a metal wiring pattern 13 and connection electrode pads 14.

接続用電極パッド１４は、チップダイレクト実装用の接
続用電極であり、第３メタル配線層のこれら接続用電極
パッド１４と第１メタル配線層の接続用電極パッド１１
とがメタル配線パターン１３によって電気的に接続され
ている。なお、第１図において、接続用電極パッド１１
及び１４の形状は四角と丸で表されているが、これらは
両者の区別を容易にするために便宜的に行われているも
のであり、実際の形状はこれらと異なる。The connection electrode pads 14 are connection electrodes for chip direct mounting, and these connection electrode pads 14 of the third metal wiring layer and the connection electrode pads 11 of the first metal wiring layer
are electrically connected by a metal wiring pattern 13. In addition, in FIG. 1, the connection electrode pad 11
The shapes of and 14 are shown as squares and circles, but these are done for convenience to make it easier to distinguish between the two, and the actual shapes are different from these.

上述したように、第３メタル配線層のメタル配線パター
ン１３によって、第１メタル配線層の接続用電極パッド
ＩＩから第３メタル配線層の接続用電極パッド１４まで
配線されているため、通常実装用ＬＳＩとチップダイレ
クト実装用ＬＳＩとを共用することができる。As described above, wiring is provided from the connection electrode pad II of the first metal wiring layer to the connection electrode pad 14 of the third metal wiring layer by the metal wiring pattern 13 of the third metal wiring layer, so that the wiring pattern 13 of the third metal wiring layer is used for normal mounting. The LSI and chip direct mounting LSI can be used in common.

このため、通常実装用ＬＳＩを開発し、それをチップダ
イレクト実装用ＬＳＩ化することが可能となり、−度に
２機種のＬＳＩ開発が行えることとなる。しかも、ワイ
ヤボンディング法によって全ての接続用電極パッドの結
線を行うことができるので、そのＬＳＩの特性試験を容
易にかつ迅速に行うことができる。For this reason, it is possible to develop an LSI for normal mounting and convert it into an LSI for chip direct mounting, making it possible to develop two types of LSI at a time. Moreover, since all the connection electrode pads can be connected by the wire bonding method, the characteristic test of the LSI can be easily and quickly performed.

しかも、既存の通常実装用ＬＳＩのチップダイレクト実
装用ＬＳＩ化及び既存のチップダイレクト実装用ＬＳＩ
の通常実装用ＬＳＩ化を図ることが可能となるため、開
発期間の短縮化、開発機種数の減少化及びチップサイズ
の縮小化が行え、効率の良いＬＳＩ開発を行うことが可
能となる。Furthermore, existing normal mounting LSIs can be converted into chip-direct mounting LSIs, and existing chip-direct mounting LSIs can be
Since it is possible to convert the device into an LSI for normal mounting, the development period can be shortened, the number of developed models can be reduced, and the chip size can be reduced, making it possible to carry out efficient LSI development.

また、第２メタル層１２が一定の電位に維持されている
ため、第１メタル配線層と第３メタル配線層との間のク
ロストークを抑制することができるという非常に大きな
利便が得られる。Further, since the second metal layer 12 is maintained at a constant potential, it is possible to suppress crosstalk between the first metal wiring layer and the third metal wiring layer, which is very convenient.

しかも、第２メタル層Ｉ２を電源配線層とすることも可
能であるため、電源配線に関するＬＳＩ設計の自由度が
大幅に大となる。Moreover, since the second metal layer I2 can also be used as a power supply wiring layer, the degree of freedom in LSI design regarding power supply wiring is greatly increased.

［発明の効果］ 以上詳細に説明したように本発明によれば、半導体チッ
プ上に設けられた第１メタル配線層の複数の電極と、半
導体チップ上の少なくとも一部に設けられており所定電
位に設定された第２メタル層と、第２メタル層上に設け
られたチップダイレクト実装用の複数の電極パッドを有
しておりこれら複数の電極パッドと第１メタル配線層の
前述の複数の電極とを接続する第３メタル配線層とを備
えているため、通常実装用ＬＳＩを電気的特性変化を与
えることなく共用することが可能なチップダイレクト実
装による半導体装置を得ることができる。[Effects of the Invention] As described above in detail, according to the present invention, the plurality of electrodes of the first metal wiring layer provided on the semiconductor chip and the electrodes provided on at least a portion of the semiconductor chip are connected to a predetermined potential. and a plurality of electrode pads for chip direct mounting provided on the second metal layer, and these electrode pads and the aforementioned plural electrodes of the first metal wiring layer. Since the third metal wiring layer is provided for connecting the semiconductor device and the third metal wiring layer, it is possible to obtain a semiconductor device by chip direct mounting, in which an LSI for normal mounting can be shared without changing the electrical characteristics.

その結果、既存の通常実装用ＬＳＩをチップダイレクト
実装用ＬＳＩ化することが可能であり、しかも同時に２
機種の開発が行える。また、全ての接続用電極パッドに
ついて特性試験を容易にかつ迅速に行うことができるた
め、開発期間の短縮化、開発機種数の減少化を図ること
ができ、産業上非常に有効である。As a result, it is possible to convert an existing normal mounting LSI into a chip direct mounting LSI, and at the same time, two
Ability to develop models. Furthermore, since characteristic tests can be easily and quickly performed on all connection electrode pads, it is possible to shorten the development period and reduce the number of developed models, which is very effective industrially.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例の構成を概略的に示す平面図
である。 １０・・・・・・ＬＳＩチップ、１１、Ｉ４・・・・・
・接続用電極パッド、１２・・・・・・第２メタル層、
１３・・・・・・メタル配線パターン。FIG. 1 is a plan view schematically showing the configuration of an embodiment of the present invention. 10... LSI chip, 11, I4...
・Connection electrode pad, 12...second metal layer,
13...Metal wiring pattern.

Claims (1)

【特許請求の範囲】[Claims] 　半導体チップ上に設けられた第１メタル配線層の複数
の電極と、該半導体チップ上の少なくとも一部に設けら
れており所定電位に設定された第２メタル層と、該第２
メタル層上に設けられたチップダイレクト実装用の複数
の電極パッドを有しており該複数の電極パッドと前記第
１メタル配線層の前記複数の電極とを接続する第３メタ
ル配線層とを備えたことを特徴とする半導体装置。a plurality of electrodes of a first metal wiring layer provided on the semiconductor chip; a second metal layer provided on at least a portion of the semiconductor chip and set to a predetermined potential;
A third metal wiring layer having a plurality of electrode pads for chip direct mounting provided on a metal layer and connecting the plurality of electrode pads and the plurality of electrodes of the first metal wiring layer. A semiconductor device characterized by:
JP2107160A 1990-04-23 1990-04-23 Semiconductor device Expired - Lifetime JP2533810B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2107160A JP2533810B2 (en) 1990-04-23 1990-04-23 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2107160A JP2533810B2 (en) 1990-04-23 1990-04-23 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH045841A true JPH045841A (en) 1992-01-09
JP2533810B2 JP2533810B2 (en) 1996-09-11

Family

ID=14452017

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2107160A Expired - Lifetime JP2533810B2 (en) 1990-04-23 1990-04-23 Semiconductor device

Country Status (1)

Country Link
JP (1) JP2533810B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7288846B2 (en) 1997-09-11 2007-10-30 Oki Electric Industry Co., Ltd. Semiconductor chip having pads with plural junctions for different assembly methods

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7288846B2 (en) 1997-09-11 2007-10-30 Oki Electric Industry Co., Ltd. Semiconductor chip having pads with plural junctions for different assembly methods
US7309915B2 (en) 1997-09-11 2007-12-18 Oki Electric Industry Co., Ltd. Semiconductor chip having pads with plural junctions for different assembly methods
US7344968B2 (en) 1997-09-11 2008-03-18 Oki Electric Industry Co., Ltd. Semiconductor chip having pads with plural junctions for different assembly methods

Also Published As

Publication number Publication date
JP2533810B2 (en) 1996-09-11

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