JPH0458566A - Nonvolatile storage device and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable a production process to be simplified by forming a gate region of a storage element in an element-forming region on a substrate and at the same time by forming a gate region of an address element in one piece through at a sidewall side of the same gate region through a breakdown strength oxide film. CONSTITUTION:Thick field insulating films 2a and 2b are formed, thus forming an element formation region 3. Then, a gate insulating film 4a is formed and a silicon nitriding film 4b and a polycrystalline silicon film 4c are laminated and then a gate region for storage element 4 is formed leaving only the gate electrode part only by etchback. Then, after laminating a gate insulation film 5a and a polycrystalline silicon film 5b, etching treatment is performed and gate regions for address element 5A and 5B are formed. Then, an n<+> source region 7S and a drain region 7D are formed outside. Then, a contact hole 11 is formed and then an aluminum thin film 12 for wiring is subjected to vacuum deposition onto it. Further, after forming gate wiring 4d and 5c, a source wiring 13s, and a drain wiring 13d, a bonding pad 15 is provided.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electrically erasable nonvolatile memory device comprising a memory element and an address element, and a method for manufacturing the same.

[Conventional technology]

As this type of electrically erasable nonvolatile memory device, there is a trap as described on pages 495 to 498 of "Semiconductor Handbook, 2nd Edition, 6th Printing (published by Ohm Publishing)". They are broadly classified into level storage type and floating gate storage type.

In order to use this electrically erasable non-volatile memory device as a semiconductor memory, it is possible to use an L element/pinto configuration in which one memory transistor constitutes one bit, or one transistor memory and one MOSFET. A two-element/bit configuration has been proposed in which one bit is composed of two elements.

Here, in the case of a 1-element/bit configuration, the logical values "0" and "1" due to writing and erasing of the memory transistor are defined by the threshold voltages of the depletion mode and the enhancement mode, so the gate voltage in the depletion mode Since the drain current flows when the voltage is zero, a two-element/bit configuration has recently become mainstream.

As a nonvolatile memory device with this two-element/focus configuration,
A first field effect transistor as a memory element and a second field effect transistor as an address element are connected in series on a semiconductor substrate, and the address element is configured to block drain current in a depletion mode. There is.

[Problem to be solved by the invention]

However, in the above-mentioned conventional nonvolatile memory device with a two-element/bit configuration, it is necessary to form the memory element and the address element separately, which increases the number of manufacturing steps and reduces the cell area of the nonvolatile memory device. However, there were unresolved problems such as difficulty in increasing the capacity and increasing chip cost.

Therefore, the present invention has been made by focusing on the unresolved problems of the conventional example, and it is possible to reduce the cell area, simplify the manufacturing process, and perform large-scale integration. It is an object of the present invention to provide a nonvolatile memory device with a two-element/bit configuration that allows for a two-element/bit configuration, and a method for manufacturing the same.

[Means to solve the problem]

In order to achieve the above object, a nonvolatile memory device according to claim (1) is an electrically erasable nonvolatile memory device comprising a memory element and an address element. In addition to forming the gate region of the memory element, the gate SN region of the address element is integrally formed on the side wall side of the memory element gate region with a voltage resistant oxide film interposed therebetween.

Further, a method for manufacturing a non-volatile memory device according to claim (2) is a method for manufacturing an electrically erasable non-volatile memory device comprising a memory element and an address element, in which a field insulating film is formed on a semiconductor substrate. After forming a relatively thin gate insulating film and forming a first polycrystalline silicon film on the gate insulating film via a silicon nitride film or an aluminum oxide film, gate patterning is performed to form the memory element gate region. A relatively thick oxide film having voltage resistance is formed to cover the gate insulating film and the memory element gate region, and a second polycrystalline silicon film is formed on the oxide film. The second polycrystalline silicon film is anisotropically etched back to leave only a portion corresponding to the sidewalls of the gate region for the memory element to form the gate (SN) region for the address element, and then the semiconductor substrate is doped with impurities. It is characterized by spreading.

[Effect]

In the nonvolatile memory device according to claim (1), since the address element gate region is integrally formed on the side wall of the SN region, the address element is formed during the manufacturing process of the memory element. In addition, the cell area can be significantly reduced compared to conventional examples, and miniaturization is possible, so large-scale integration can be achieved, and gate insulation of memory elements and address elements can be reduced. By changing the film thickness, enhancement mode operation can be performed, and the number of wiring lines can be reduced by using a common gate electrode for the memory element and the address element.

Further, in the method for manufacturing a nonvolatile memory device according to claim (2), after forming a gate SN region of a memory element on a semiconductor substrate, an insulating film and a polycrystalline silicon film are formed to form a polycrystalline silicon film. Since the address element gate 9M region is formed by anisotropically etching back the film, the memory element and address element can be integrally formed on the semiconductor substrate, simplifying the manufacturing process. can be converted into

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a cross-sectional view showing an embodiment of the present invention, in which a memory element gate 6 is located in the center of an element forming region 3 separated by field insulating films 2a and 2b on a p-type silicon substrate 1.
An M region 4 is formed, and address element gate regions 5A are formed on both sides thereof.

5B are formed, these are covered with a protective film 6, and a source region 78 and a drain region 7D of N'' are formed on the silicon substrate 1 to constitute an electrically erasable nonvolatile memory device 8. .

Here, the memory element gate 9M region 4 is located on the silicon substrate 1.
For example, a thin gate insulating film 4 of about 20 layers is formed on the
a, and for example 300 formed on this gate insulating film 2.
A silicon nitride film 4b composed of approximately 500 nano-sized ions (Si, N,), a polycrystalline silicon film 4C formed on the silicon nitride film 4b, and a polycrystalline silicon film 4C formed on the polycrystalline silicon film 4C. It has a configuration of a so-called n-channel MNOS memory.

Further, the address element gate regions 5A and 5B are formed on the aforementioned gate insulating film 4a and on the sidewalls of the memory element gate region 4 and are relatively thick (for example, 300 to 1000 mm thick).
) A gate insulating film 5a made of a CVD 5in2 film,
A memory element gate region 4 is in contact with this gate insulating film 5a.
It is composed of a polycrystalline silicon film 5b along the polycrystalline silicon film 5b, and a gate wiring 5c connected to the gate wiring 4d formed on the polycrystalline silicon film 5b, and has the configuration of an n-channel MoS transistor.

In FIG. 1, 13s is a source wiring, 13d is a drain wiring, 14 is a protective oxide film, and 15 is a bonding pad.

Next, a method for manufacturing the nonvolatile memory device 8 having the above configuration will be explained with reference to FIG.

First, a p-type silicon substrate 1 containing boron as an impurity is prepared, and on the surface of this silicon substrate 1, for example, LOCO3 is applied.
An element forming region 3 is formed by forming thick field insulating films 2a and 2b by a method (see FIG. 2(a)).

Next, a gate insulating film 4a made of a thin silicon oxide film of about 20 layers is formed on the surface of the silicon substrate 1 by drying, for example.
A silicon nitride film 4b made of nitride is formed on this gate insulating film 4a to a precise thickness by an oxidation method, and then a silicon nitride film 4b made of nitride is formed to a thickness of about 300 to 500 layers on this silicon nitride film 4b. After stacking the polycrystalline silicon film 4C that will become the gate electrode to a thickness of about several thousand layers, the gate region 4 for the memory element is formed by etching back and leaving only the gate electrode portion (see Fig. 2). (′
b)).

Next, the gate insulating film 4a and the memory element gate? iJ
A gate insulating film 5a made of a relatively thick (approximately 300 to 1,000 thick) siliconized film is formed by the CVD method so as to cover the f region 4 so as to obtain a predetermined dielectric strength characteristic. A polycrystalline silicon film 5b is formed thereon (see FIG. 2(C)).

Next, polycrystalline silicon film 5b and silicon oxide film 5a are formed.
By anisotropic etching, only the polycrystalline silicon film 5b corresponding to the sidewalls of the memory element gate region 4 is left to form an address element gate region 5A5B (see FIG. 2(C)).
)reference).

Next, using the memory element gate region 4 and the address element gate regions 5A and 5B as masks, the source region 7S and drain region 7D of n' are formed by thermally diffusing phosphorus or ion-implanting arsenic into the silicon substrate 1. , are formed outside the address element gate regions 5A and 5B (see FIG. 2(e)).

Next, on the gate insulating film 4a, the memory element gate region 4, and the address element gate 6N regions 5A and 5B, a glabellar insulating film 10 for performing multilayer wiring is formed by CVD. memory element gate region 4;
Address element gate 9M areas 5A, 5B, source area 6
Contact holes 1 are formed at positions corresponding to S and drain regions 6D, and a thin aluminum film 12 for wiring is vacuum-deposited thereon (see FIG. 2).

Next, the aluminum thin film 12 is removed by etching, leaving only the necessary wiring portions using photolithography technology, and forming a memory element gate.
Gate wirings 4d and 5C, source wiring 13s, and drain wiring 13d connecting the II region 4 and address element gate regions 5A and 5B are formed, and then an aluminum thin film 1 is formed.
After forming an oxide film 14 as a protective film on 2 by CVD method, bonding pads 15 for connecting each electrode 4d, 13s, and 13d to the outside are formed to form the intended nonvolatile memory device 8. obtain.

In this way, according to the above embodiment, the memory element gate region 4 and the address element gate 6 are provided in one element formation region 3.
Since the 14 regions 5A and 5B are formed, two address MOS transistors 22A and 22B are connected in series on both sides of the memory MNO transistor 21, equivalently as shown in FIG. , and these gate electrodes G are connected to each other, and by adjusting the film thickness of the gate insulating films 4a and 5a of each gate region 4.5A and 5B, a memory can be formed as shown in FIG. for MN
OS) For example, set the threshold voltage VTM of the transistor 21 to +7■
Then, the dark value voltage VTA of the address MO3) transistors 22A and 22B can be set to +1, for example, to operate in the enhancement mode.

Therefore, when writing, a gate voltage of +20V, for example, is applied to the gate electrode G. By applying , electrons are injected from the silicon substrate 1 side by tunnel transition into the silicon nitride film 4b through the thin gate insulating film 4a of the memory element gate region 4 constituting the memory MNO3I-transistor 21. A part of it is captured in the trap level between the gate insulating film 4a and the silicon nitride film 4b, so that the dark value voltage VT is set to, for example, +7■.

At this time, address MO3) transistor 22A.

22B address element game) 911 area 5A
.

+20V is also applied to 5B, but the silicon substrate 1
Since the insulating film 5a between the transistor and the polycrystalline silicon film 5b is thick, a normal transistor operation is performed without causing tunnel transition.

In addition, when erasing is performed, electrons captured in the trap level are erased by applying a negative gate voltage 6 to the gate electrode G, so that the dark value voltage Va becomes -7, for example.
set to V.

Furthermore, when performing successive addition, the gate electrode G, for example, +
5■Gate voltage■. By applying , both address MO3 transistors 22A and 22B are turned on, and at this time, when the memory MNOS transistor 21 stores the logic value Pa1, its threshold voltage 7.4 becomes +7. (2) Therefore, no current flows between the source and drain, and when the logical value "0" is stored, the dark value voltage V? Since M is 17, current flows between the source and drain.

When the voltage (2) applied to the gate electrode G is zero, the address MOS transistors 22A, 22
Since B remains off, leakage current can be reliably prevented from flowing.

As a result of (2), according to the above embodiment, the memory element and address element are integrated, so the cell area of the nonvolatile memory device can be miniaturized, and the gate electrode can be shared, reducing the number of wiring lines. It can also be operated in enhancement mode.

Note that in the above embodiment, MNOS is used as the memory element.
) The case where the transistor 21 is applied was explained, but
The invention is not limited to this, and instead of the silicon nitride film 4b of the memory element gate region 4, alumina (Al z
By applying an O3) film, a MAOS transistor can be obtained.

Further, in the above embodiment, a case has been described in which the gate electrodes of the gate region for a memory element and the gate region for an address element are connected to each other, but the invention is not limited to this. Gate electrodes in the fiI region may be provided independently.

Furthermore, although the case where the present invention is applied to a trap level accumulation type nonvolatile memory device has been described, the present invention can also be applied to a floating gate accumulation type nonvolatile memory device.

[Effects of the Invention] As explained above, according to the nonvolatile memory device according to claim (1), an address element is provided in the element formation region on the semiconductor substrate via an insulating film on both sides of the memory element gate region. Since a cell structure is formed in which a memory element and an address element are integrated by forming a gate region, it is possible to miniaturize the cell area, achieve large-scale integration, and also form a cell structure in which a memory element and an address element are integrated. The gate electrodes of the device can be connected to each other to reduce the number of wiring lines, and the device can be operated in an enhancement mode.

Further, according to the method for manufacturing a nonvolatile memory device according to claim (2), after forming the gate region for a memory element, the gate insulating film of the gate region for an address element, the insulating film to be a gate electrode, and the polycrystalline silicon Since the gate region for the address element is formed by forming a film and anisotropically etching it back, the process for forming the gate region for the address element is not complicated (it is easy to use non-volatile The effect of being able to manufacture a storage device is obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing an embodiment of a nonvolatile memory device according to the present invention, FIGS. 2(a) to (f) are process diagrams showing a method for manufacturing a nonvolatile memory device according to the present invention, and FIG. FIG. 4 is an equivalent circuit diagram of the nonvolatile memory device according to the present invention, and is a characteristic diagram showing drain current versus gate voltage of the nonvolatile memory device according to the present invention. In the figure, 1 is a silicon substrate (semiconductor substrate) and 2a. 2b is a field insulating film, 3 is an element formation region, 4 is a memory element gate) 9M area, 5A, 5B are address element gate regions, 4a is a gate insulating film, 4b is a silicon nitride film, 4c is a polycrystalline silicon film , 5a is a gate insulating film, 5b
is a polycrystalline silicon film, 7s is a source region, and 7D is a drain region.

Claims (2)

[Claims] (1) In an electrically erasable nonvolatile memory device composed of a memory element and an address element, a gate region of the memory element is formed in an element formation region on a semiconductor substrate, and a gate region for the memory element is formed in an element formation region on a semiconductor substrate. 1. A nonvolatile memory device characterized in that a gate region of the address element is integrally formed on a side wall side of the region with a voltage-resistant oxide film interposed therebetween. (2) In a method of manufacturing an electrically erasable nonvolatile memory device composed of a memory element and an address element, a field insulating film and a relatively thin gate insulating film are formed on a semiconductor substrate, and the gate insulating film After forming a first polycrystalline silicon film thereon via a silicon nitride film or an aluminum oxide film, gate patterning is performed to form the memory element gate region, and then a gate insulating film and a memory element gate region are formed. A relatively thick oxide film having pressure resistance is formed to cover the oxide film, and a second polycrystalline silicon film is formed on the oxide film, and then the second polycrystalline silicon film is anisotropically etched back. A method for manufacturing a nonvolatile memory device, characterized in that the address element gate region is formed by leaving only a portion corresponding to a side wall of the memory element gate region, and then impurities are diffused into the semiconductor substrate.