JPH0458899U - - Google Patents
Info
- Publication number
- JPH0458899U JPH0458899U JP10053090U JP10053090U JPH0458899U JP H0458899 U JPH0458899 U JP H0458899U JP 10053090 U JP10053090 U JP 10053090U JP 10053090 U JP10053090 U JP 10053090U JP H0458899 U JPH0458899 U JP H0458899U
- Authority
- JP
- Japan
- Prior art keywords
- adder
- output end
- input end
- diode
- delay device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Measurement Of Current Or Voltage (AREA)
Description
第１図は本考案の実施例の回路図、第２図は第
１図の動作を例示するタイミングチヤート、第３
図は従来のピークホールド回路の回路図、第４図
ａ〜ｃは第３図の動作を例示するタイミングチヤ
ートである。
１……外部入力端子、２……加算器、３……遅
延器、４……ダイオード、５……コンデンサ、６
……外部出力端子、７……バツフア。
FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a timing chart illustrating the operation of FIG. 1, and FIG.
The figure is a circuit diagram of a conventional peak hold circuit, and FIGS. 4a to 4c are timing charts illustrating the operation of FIG. 3. 1... External input terminal, 2... Adder, 3... Delay device, 4... Diode, 5... Capacitor, 6
...External output terminal, 7...Buffer.
Claims (1)
入力端を前記加算器の出力端に接続し出力端を前
記加算器のもう一方の入力端に接続した遅延器と
、前記遅延器の出力端をアノードに接続したダイ
オードと、前記ダイオードのカリードと外部出力
端子とを接続する信号線に並列に接続したコンデ
ンサとを備えていることを特徴とするピークホー
ルド回路。 an adder with an input signal connected to one input end;
a delay device whose input end is connected to the output end of the adder and whose output end is connected to the other input end of the adder; a diode whose output end is connected to the anode of the delay device; and a calyde of the diode. A peak hold circuit characterized by comprising a capacitor connected in parallel to a signal line connecting an external output terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10053090U JPH0458899U (en) | 1990-09-26 | 1990-09-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10053090U JPH0458899U (en) | 1990-09-26 | 1990-09-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0458899U true JPH0458899U (en) | 1992-05-20 |
Family
ID=31843256
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10053090U Pending JPH0458899U (en) | 1990-09-26 | 1990-09-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0458899U (en) |
-
1990
- 1990-09-26 JP JP10053090U patent/JPH0458899U/ja active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH0458899U (en) | ||
| JPS61103969U (en) | ||
| JPS60172434U (en) | Malfunction prevention circuit at startup | |
| JPS5840939U (en) | Isolated buffer circuit | |
| JPS58139717U (en) | Muting circuit | |
| JPH0195828U (en) | ||
| JPS60181926U (en) | signal generation circuit | |
| JPS58522U (en) | Pulse width shaping circuit | |
| JPS588168U (en) | AD conversion circuit for resistance sensor | |
| JPS593447U (en) | ultrasonic pulse switch | |
| JPS62151238U (en) | ||
| JPS5890749U (en) | Waveform shaping circuit | |
| JPS5830442U (en) | low frequency treatment device | |
| JPS58107633U (en) | Output circuit | |
| JPS6344165U (en) | ||
| JPH0397236U (en) | ||
| JPS5976141U (en) | level conversion circuit | |
| JPS60143685U (en) | Signal transmission device with robot's replaceable hand | |
| JPH01151625U (en) | ||
| JPS5873613U (en) | Class A audio output circuit | |
| JPS643336U (en) | ||
| JPS61119430U (en) | ||
| JPS60148634U (en) | Asynchronous trigger generator | |
| JPS61174227U (en) | ||
| JPS5857918U (en) | Highest point holding circuit |