JPH0459655U

JPH0459655U -

Info

Publication number: JPH0459655U
Application number: JP10140790U
Authority: JP
Priority date: 1990-09-27
Filing date: 1990-09-27
Publication date: 1992-05-21

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例を示す構成ブロツク
図、第２図は判定回路を論理回路で構成した場合
の一例を示す回路図、第３図は動作を示すタイム
チヤート、第４図は本考案の他の実施例を示す構
成ブロツク図、第５図、第６図は第４図回路の各
部の動作を示すタイムチヤート、第７図は従来装
置の構成ブロツク図、第８図はその動作を示すタ
イムチヤートである。ＳＲ……シフトレジスタ部、ＨＣ……判定回路
、Ｆ／Ｆ……フリツプフロツプ、Ｇ１〜Ｇ３，Ｇ
５……ゲート、ＬＡ……ラツチ用フリツプフロツ
プ。 Fig. 1 is a configuration block diagram showing one embodiment of the present invention, Fig. 2 is a circuit diagram showing an example of a case where the judgment circuit is configured with a logic circuit, Fig. 3 is a time chart showing the operation, and Fig. 4 is A configuration block diagram showing another embodiment of the present invention, FIGS. 5 and 6 are time charts showing the operation of each part of the circuit in FIG. 4, FIG. 7 is a configuration block diagram of a conventional device, and FIG. This is a time chart showing the operation. SR...Shift register section, HC...Judgment circuit, F/F...Flip-flop, G1 to G3, G
5...Gate, LA...Flip-flop for latch.

Claims

[Claims for Utility Model Registration] A shift register section that sequentially shifts input signals using a clock and outputs each of the shifted signals, and each signal A1, A2,...An output from this shift register section. When the output signal Ao output by itself is input, and all of the signals A1, A2, ...An output from the shift register section are at high level, the output signal Ao is set to high level, and each signal A1, A2, ...a determination circuit that sets the output signal Ao to a low level when all of An are at a low level, and does not change the output signal Ao at other times than the above, and by adjusting the number of stages of the shift register, a specific A digital noise removal device characterized by removing noise components having a pulse width or less regardless of their periodicity.