JPH046028B2 - - Google Patents

Abstract

PURPOSE:To realize an automatic monitoring by converting an address to an address data in a CPU through a data bus line of an externally fitted memory, and extracting a corresponding data in its built-in memory by loading it on an address bus. CONSTITUTION:In an automobile engine controlling microcomputer, the first memory 2 contained in a central processor 7 provided with the second memory 8 which can be attached and detached is monitored by a data collecting CPU17. In that case, the CPU17 is constituted of an address storage means 30 and a monitoring means 33, and connected to each data and address bus 8a, 8b of the memory 8 through a transfer means 31. In this state, the means 31 transfers an address in the means 30 at a prescribed timing to a data bus 3 of the device 7 through the bus 8a, converts it to an address data by a control means 32, loads a corresponding data in the memory 2 on an address bus 4, extracts a data by the means 33 through the bus 8b, and stops the means 32.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a monitoring device for a memory built into a central processing unit.

[Prior art]

In recent years, it has become common practice in automobiles to control engine ignition timing, air-fuel ratio, etc. using microcomputers. In the development stage of various control devices for such automobiles, in order to evaluate the control programs, it is necessary to extract various data of the automobile such as engine cooling water temperature.
As a method of sequentially extracting various data of a car in this way, for example, as shown in Japanese Patent Laid-Open No. 57-22302, data is collected from various sensors that detect the driving state of the car and stored. I found a way to go. However, this method has the problem that in addition to wiring for guiding various signals from the various sensors to the control device, that is, the control unit, wiring for monitoring must be connected, making the structure complicated.

By the way, in the above-mentioned control device, there is a place in the CPU that stores the output of various sensors such as the above-mentioned cooling water temperature, and if you monitor this, you can connect the monitoring line from the sensor as described above. No need to strain. However, in the control device installed in an actual vehicle, a mask type one-chip CPU is used as the CPU.
This 1-chip CPU has program memory (ROM) and work memory (RAM) built into the 1-chip, and the data bus and address bus do not go out to the outside.
There was a problem that the state of the contents could not be seen.

Therefore, the following two methods have been used as conventional countermeasures for this problem.

The first method is to use a 1-chip CPU with a built-in PROM at the development stage, that is, a 1-chip CPU with a built-in ROM that can be rewritten using a special method such as erasing ultraviolet light. This method involves changing the program sequentially, but this method has the problem that although the program can be changed, the internal RAM cannot be monitored, and since the program must be changed sequentially, it requires a large amount of effort. This requires development man-hours.

The second method was to use an evaluation board. This involves removing a 1-chip CPU from a control unit installed in a car, and inserting a board that is pin-compatible with this 1-chip CPU.
This method involves building a circuit on this board that can use a general-purpose PROM that has the same functionality as a single-chip CPU. And one chip on a board like this
The idea is to install a CPU, use it in an expansion mode where a data bus and address bus come out like a general-purpose CPU, and use this data bus and address bus to monitor the internal RAM of a single-chip CPU. be.

However, with this method, the internal RAM is monitored when the 1-chip CPU is used in expansion mode, which is different from the actual usage mode installed in the actual vehicle, so the software also needs to be modified slightly. However, there was a drawback that the evaluation in this extended mode was not the final evaluation. Another drawback was that it required work to attach an evaluation board, which was time-consuming.

By the way, among the conventional 1-chip CPUs, there is a piggyback type 1-chip CPU, in which only the ROM is taken out from the 1-chip CPU, and the baby turtle is placed on top of the parent turtle, excluding the ROM. It has a ROM mounted on a single-chip CPU. And a piggyback type chip like this
Since the CPU can use general-purpose PROM instead of ROM, programs can be modified, and since the data bus and address bus are visible to the outside,
It is expected that internal RAM data can be easily monitored. However, in this piggyback type single-chip CPU, the internal
Even if you try to monitor the RAM, the only address buses and data buses that are visible to the outside are the outward address bus that goes to the external ROM and the inward data bus that goes into the chip. Since there was no outward-facing address bus or outward-facing data bus, it was not possible to easily monitor the internal RAM.

The applicant focused on the fact that in the above-mentioned piggyback type one-chip CPU, an address bus and a data bus appear at the input/output terminals of the external ROM.
The address of the built-in memory to be monitored is input to the data bus of the external ROM of the CPU, and the data on the data bus is converted into address data by the arithmetic unit inside the chip, which specifies the address of the built-in memory. We have already developed a monitoring method that converts the read data into address data, puts it on the address bus of an external ROM, and retrieves the data in the built-in memory from this address bus (Japanese Patent Application No. 58-49959). ).

[Purpose of the invention]

The present invention has been made under such circumstances, and is intended to provide a monitoring device for a memory built into a central processing unit, which is one device for realizing the monitoring method developed by the applicant.

[Structure of the invention]

Therefore, in the present invention, as shown in the functional block diagram of FIG. The data on the data bus is transferred to the data bus in the central processing unit 7 via the data bus line of the memory 8, and the control means 32 converts the data on the data bus into address data and the data in the first memory 2 corresponding to the address data. The data is converted into address data in a specific format and placed on the address bus, and the monitoring means 33 takes out the address data in the specific format from the address bus line of the second memory 8 and converts the address data into the address data in the first memory. The stopping means 34 stops the processing by the control means 32 when the transfer means 31 transfers the specified data.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

2 and 3 show a monitoring device for a memory built into a central processing unit according to an embodiment of the present invention.
Figure 2 shows a piggyback type 1-chip CPU that attempts to monitor its built-in memory.
In the figure, numeral 1 normally executes programs for various controls of the automobile, and when a predetermined timing comes, executes the program shown in the flowchart of FIG. 4, and numeral 2 detects the driving state of the automobile. A rewritable calculation unit that stores information from various sensors and intermediate results of execution of the calculation unit 1, etc.
RAM (first memory), 3 is an 8-bit data bus, 4 is a 16-bit address bus, 5 is a data input circuit, 6 is an address output circuit, 7 is a chip equipped with these circuits 1 to 6, 8 is an EPROM (second memory) externally attached to chip 7.
In the storage area of the EPROM 8 at addresses F800 to FFFF, programs for various controls and programs for executing the flow shown in FIG. 4 are stored. Further, the data bus 8a and address bus 8b of the EPROM 8 are connected to the data input circuit 5 and address output circuit 6. Note that 9 to 1 in the figure
2 are input/output circuits, P10 to P17,
P20 to P24, P30 to P37, and P40 to P47 are input/output ports connected to the input/output circuits 9 to 12, respectively. Also, 13 is SCI, 14 is a timer circuit,
15 is a mode circuit, and 16 is a multiplexer.

FIG. 3 shows the monitoring device of this embodiment. In the figure, 8 has the above-mentioned EPROM, 17 has a plurality of addresses to be monitored in the RAM 2, and data for executing the program shown in the flowcharts of FIGS. 5 and 6. A collection CPU, 18 is a first gate circuit that puts the address appearing at the output port 17a of the CPU 17 onto the data bus 8a of the EPROM 8, and 19 is a first gate circuit;
An RS flip-flop receives the control signal ACK from the CPU 17 as a set input, 20 is a second gate circuit that puts the Q output of the flip-flop 19 on the data bus 8a of the EPROM 8, and 21 is the lower 8 bits of the address data from the address bus 8b of the EPROM 8. and connect it to input port 1 of CPU17.
7b, and 22 is a decoder/timing circuit, which receives the first address data from the address bus of EPROM 8, for example, F0×× (× is 0
~ Any number of F) is read, the above 1st
generates a control signal a that opens the gate circuit 18;
When the third address data, for example F1XX, is read, the control signal b is generated to activate the latch circuit 21 and reset the RS flip-flop 19, and when the third address data, for example F2XX, is read. is the second above
A control signal c is generated to open the gate circuit 20, and the control signal b is further transmitted to the CPU.
17 interrupt terminal 17c. Note that this is an enable signal for adjusting the timing at which data is placed on the data bus 8a from the first and second gate circuits 18 and 20.

In the above configuration, the arithmetic unit 1 realizes the functions of the control means 32 and the stop means 34 shown in FIG.
The CPU 17 realizes the functions of the address storage means 30 and the monitoring means 33 shown in FIG.
The first and second gate circuits 18, 19, flip-flop 20 and decode timing circuit 22
constitutes the transfer means 31 in FIG.

Next, the general operation of this device will be explained.

The data collection CPU 17 is initially in the state of step 50 in FIG.
Then (step 35 in FIG. 4), the decode/timing circuit 22 receives address data via the address bus line 8b of the EPROM 8, decodes that the data is F0XX, and sends the first gate circuit 18. Open the built-in device you want to monitor.
The 8-bit address in RAM2 is used for data collection.
Data bus line 8 from CPU 17 to EPROM 8
The data is transferred to the data bus 3 within the 1-chip CPU via a. The arithmetic unit 1 then reads the transferred 8-bit address, converts it into 16-bit address data, addresses RAM2 with the 16-bit address data, reads out the 8-bit data in RAM2, and then reads the 8-bit data in RAM2. The 8-bit data is placed on the lower 8 bits of the 16-bit data F1xx, and the 16-bit data is placed on the address bus 4 (steps 35 to 41 in FIG. 4). The 16-bit data is then processed by the decode/timing circuit 22.
When received via the address bus line 8b of the EPROM 8 and decoding that this is F1XX, the latch circuit 21 extracts the data in RAM2 from the lower 8 bits of the 16-bit data F1XX and uses it for data collection. Provided to CPU17 for data collection
The CPU 17 reads the data in the RAM 2 and stores it (steps 51 and 52 in FIG. 6).

When one piece of data in the RAM 2 is monitored in this way, the arithmetic unit 1 then puts the address data F2XX onto the address bus 4 (steps 43 and 44 in FIG. 4), and the decode/timing circuit 22
receives the address data and decodes that it is F2XX, the second gate circuit 20 opens,
Q output of flip-flop 19 is 1 chip CPU
The data is transferred to the data bus 3 within. If the data monitoring is not completed, the Q output of the flip-flop 19 becomes "1" by the control signal ACK from the data collection CPU 17, and the arithmetic unit 1
reads the above Q output “1” and repeats the above-mentioned processing for monitoring, and when the monitoring of the necessary data is completed, the CPU 1 for data collection
Since the control signal ACK is not output from 7,
The Q output of the flip-flop 19 remains at "0", and the arithmetic unit 1 reads the Q output "0" and completes the processing for data collection.

Next, the operation will be explained in detail using FIGS. 4, 5, and 6.

When the data collection CPU 17 operates, the CPU
Step 17 executes the main routine shown in FIG. 5, and first performs initial settings (step 47).
After setting the address for data collection of the first channel in the output port 17a (step 48) and setting the internal state to an interrupt enabled state (step 49), various processes are performed (step 50).

On the other hand, the calculation unit 1 normally executes a control program written in the EPROM 8.
At a predetermined timing, the process moves to the data collection service routine shown in FIG. Then, the decode timing circuit 22
I read the address data F0XX appearing on the address bus 8b of the EPROM 8, and since the upper 8 bits are F0, I want to generate the control signal a, open the first gate circuit 18, and now monitor it with the data collection CPU 17. If 90 is set as the address of RAM2, this address 90 is
The arithmetic unit 1 reads the address 90 input to the data bus 8a of the EPROM 8 via the data input circuit 5 and the data bus 3 in the chip 7, and stores it in the register B. Remember.

Next, this calculation unit 1 stores 0 in register X (step 36), adds the contents of register B and the contents of register 37),
Place the address data 0090 on address bus 4.
RAM2 is addressed, data to be monitored, for example 40, is read out from RAM2 and stored in register B (step 38). Note that the reason why 0 is stored in register X in step 36 above is because the storage area of RAM2 is
This is because it is an address from 0000 to 00FF.

Furthermore, the calculation unit 1 stores F100 in register X (step 39), adds the contents of register B and the contents of register ,
The EPROM 8 is also addressed using the address data F140 (step 41). Then, the decode timing circuit 22 reads the address data F140 appearing on the address bus 8b of the EPROM 8,
Since the upper 8 bits are now F1, the control signal b is generated to operate the latch circuit 21, and the latch circuit 21 selects the lower 8 bits of the address data F140.
It latches bit data 40 and sends it to the data collection CPU 17.

The control signal b generated from the decode timing circuit 22 is also applied to the interrupt terminal 17c of the data collection CPU 17, and the CPU 17 then shifts from the main routine to the interrupt routine shown in FIG. The above data 40 is read from the input port 17b and saved (steps 51 and 52), and it is determined whether data collection for a predetermined number of addresses has been completed. If not, it is determined NO and the process proceeds to step 54. After setting the address of the next channel to the output port 17a and sending the control signal ACK (step 55), the process returns to the main routine.In this way, one piece of data in RAM2 is monitored. Then, the calculation unit 1 stores the time t in the register B (step 42), and then stores the time t in the EPROM 8.
Specify address F2XX for . Then, the decode timing circuit 22 receives the address data.
F2XX is read, and since the upper 8 bits are F2, the control signal c is generated to open the second gate circuit 20, and the output Q of the RS flip-flop 19 is
It is input to the data bus 8a of the EPROM 8, and the arithmetic unit 1 reads the output of this RS flip-flop 19 and stores it in the register A. Step 43)
It is determined whether the value of this register A is 0 (step 44). If data collection for a predetermined number of addresses has not been completed, the control signal ACK is output from the data collection CPU 17 as described above.
Since the output Q of the RS flip-flop is “1”, the arithmetic unit 1 determines NO and proceeds to the step.
Return to step 35 and repeat the above process.

Then, as described above, the data in the RAM 2 is monitored one after another, and when the data collection is completed, the data collection CPU 17 makes a YES determination in step 53 of the interrupt routine, proceeds to step 56, and selects the output port 17a. The address of the first channel is set in , and the process returns to the main routine. Then, the decode timing circuit 22 outputs the address bus line 8 of the EPROM 8.
When the address data of F2XX is read from b and the control signal b is output, flip-flop circuit 1
The Q output of 9 becomes “0”, which causes the arithmetic unit 1
is determined to be YES in step 44, and the step
Proceed to step 45, subtract 1 from the value in register B, store the result in register B, then determine whether the value in register B is 0 (step 46), and continue until the above set time t elapses. determines NO and steps
Returning to step 43, the process of steps 43 to 46 is repeated, and when the set time t has elapsed, it is determined YES in step 46, the data collection service routine process is completed, and the program for normal control is executed. I will be returning.

In the device of this embodiment as described above, the built-in RAM
data can be automatically and reliably monitored.
Furthermore, since addresses F0xx, F1xx, and F2xx that do not conflict with normal control addresses F800 to FFFF are used as addresses for RAM monitoring, normal control operations are not affected.

In the above embodiment, F0XX, F1XX, and F2XX were used as RAM monitor addresses, but F0XX, F1XX, and F2×
It may be something other than ×. Further, the position where the data is placed may be in the upper part of the address instead of the lower part.

〔Effect of the invention〕

As described above, according to the present invention, in addition to the piggyback type one-chip CPU, there is also a single chip to be monitored.
An address storage means having the address of the built-in RAM of the chip CPU, and an address storage means having the address of the internal RAM of the chip CPU;
Transfer means input to the data bus of the external ROM, and internal transfer from the address bus of the external ROM
Monitoring means for extracting RAM data is provided in the one-chip CPU, and the one-chip CPU converts the data on the data bus into address data, and also converts the data in the built-in RAM corresponding to the address data into address data. Since the present invention is equipped with a control means for placing the data on the address bus and a stop means for stopping the processing of the control means, the contents of the built-in RAM can be automatically and reliably read without affecting normal control operations. This has the effect of providing a monitoring device that can perform monitoring.

[Brief explanation of drawings]

FIG. 1 is a functional block diagram showing the configuration of the present invention.
FIG. 2 is a configuration diagram of a piggyback type one-chip CPU in which a monitoring device for the internal memory of a central processing unit according to an embodiment of the present invention is used, FIG. 3 is a configuration diagram of the above-mentioned monitoring device, and FIG. Figures 5 and 6 are flowcharts of the data collection service routine for a 1-chip CPU, respectively.
FIG. 2 is a diagram showing a flowchart of a main routine and an interrupt routine. 30...address storage means, 31...transfer means, 32...control means, 33...monitoring means,
34...Stopping means, 1...Arithmetic unit, 2...RAM
(first memory), 3...data bus, 4...address bus, 8...EPROM (second memory),
8a...Data bus line, 8b...Address bus line, 17...CPU for data collection, 18...
...first gate circuit, 19...RS flip-flop, 20...second gate circuit, 22...decode timing circuit.

Claims (1)

[Claims] 1 A device for monitoring data in the first memory in a central processing unit having a built-in rewritable first memory and removably equipped with a non-rewritable second memory, the device monitoring the data in the first memory to be monitored. an address storage means having a plurality of addresses of one memory; and a transfer means for transferring the addresses in the storage means to a data bus in the central processing unit using a data bus line of the second memory at a predetermined timing. and gives a transfer timing to the transfer means provided in the central processing unit, thereby converting the transferred data on the data bus into address data and converting the data in the first memory corresponding to the address data. control means for converting the address data into address data in a specific format and putting it on the address bus; and extracting the address data in the specific format from the address bus line of the second memory and extracting the data in the first memory from the address data. and a stop means provided in the central processing unit to stop the processing of the control means when predetermined data is transferred from the transfer means. Monitoring device.