JPH046030B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer using multiple CPUs (central processing circuits).

For example, when servo control of a VTR is performed using a microcomputer, the data for controlling is transmitted once every 1/8V (vertical period) or once every 1V.
It is taken out intermittently, such as once every. Based on this rate, one microcomputer detects the amount of data change, etc. (This means forming speed data by calculating the difference between the current data and the previous data.
Alternatively, it means distinguishing between unstable changes and definite changes in the ON/OFF data of a switch, etc., and forming it as switch data only when there is a definite change), calculating the detection results, and calculating the If control is performed according to the result, an extremely large amount of time is required to detect one piece of data and perform control, resulting in a decrease in processing capacity. Furthermore, if such processing is attempted to be performed in parallel by a microcomputer in a time-sharing manner, the operating program will become extremely complex.

In view of these points, the present invention includes a plurality of
It uses a CPU to perform high-speed processing with a simple program. Also multiple CPUs
If one of the CPUs becomes defective, it can be easily backed up to another CPU. Furthermore, data can be transferred quickly and efficiently between multiple CPUs.

An embodiment of the present invention will be described below with reference to the drawings. Note that the following explanation will be made regarding a CPU called Z-80.

That is, in FIG. 1, the first and second
CPUs 1 and 2 are provided. These CPU1,2
A circuit 3 such as a clock oscillator and a reset circuit is commonly connected to the two. Further, a read-only memory 11, a random access memory 12, an IO port 13, etc. are connected to the bus line 10 of this first CPU 1, and this bus line 10 is connected to a switch 4.
connected to. Furthermore, the bus line 20 of the second CPU 2 is connected to the switch 4.
A read-only memory 21, a random access memory 22, and an IO port 23 are connected to the bus line 20' from
4b... is connected. Furthermore, a control circuit 14 is connected to the bus line 10, and the switch 4 is switched by a signal from the control circuit 14. Note that this control circuit 14 is controlled by, for example, a predetermined address that will be described later. Also IO port 13,2
3 are connected.

Furthermore, in this circuit, addresses are assigned to CPUs 1 and 2 as shown in FIG. In other words, in the figure, if the address of the entire device is, for example, "0000" to "FFFF", the address of CPU1 is "0000" to "3FFF" and "8000" to "FFFF", and the address of CPU2 is "0000" to "FFFF". 0000” to “00FF” and “4100” to “7FFFF”. In addition, in Z-80, "0000"
From ``00FF'' to ``00FF'' contains the initial set program. Furthermore, the address of the random access memory area for data transfer of CPU1 is changed from "2E00" to "2FFF", and
Set the address of the random access memory area for data transfer from "6E00" to "6FFF".

In this circuit, switch 4 during normal operation is
It is connected to the CPU2 side, and in CPU2,
Import data through IO port 24a etc.
The process of detecting the amount of change described above is performed on this input data, the detected data is arranged into data suitable for processing by the CPU 1, and the process of storing this data in the random access memory 22. CPU1 stored in
A process of reading processing agent data and converting it into data suitable for the controlled object to form output data, and a process of outputting this output data via the IO port 24a etc. to control the controlled object (control processing) etc. In addition, CPU2 is IO port 2
The process of forming data to be written into the random access memory 22 from data read from the random access memory 22 and the process of forming output data from the data read from the random access memory 22 are called conversion processes. On the other hand, in the CPU 1, necessary arithmetic processing is performed based on the data stored in the random access memory 12, and data resulting from this processing is stored in the random access memory 12.

Furthermore, when an address from "2E00" to "2FFF" is specified by the CPU 1, the control circuit 14 switches the switch 4, and the random access memory 1
Data is transferred between 2 and 22. When the data transfer is completed, the switch 4 is returned to the illustrated position, and the above-described arithmetic processing, conversion processing, and control processing are performed.

Further, during normal times, the operations of the CPUs 1 and 2 are mutually monitored through the IO ports 13 and 23.
When the operation of CPU2 becomes abnormal, CPU1 backs up CPU2. i.e.
By specifying an address from "4100" to "7FFF" on the CPU 1, the switch 4 is switched on the control circuit 14, and the read-only memory 2 is switched on the CPU 1.
1. Random access memory 22, IO port 2
4a etc. are directly controlled. Furthermore, when the operation of the CPU 1 becomes abnormal, the CPU 2 supplies a signal to the IO port 24a etc. to stop the device, thereby preventing the occurrence of an accident.

In this way, control is performed by multiple CPUs, but according to the present invention, CPU 2 performs data conversion processing and control processing, and CPU 1 performs data arithmetic processing independently, so it is easy to use. High-speed processing can be performed with a simple operating program.

In addition, by assigning the addresses of CPUs 1 and 2 as shown in Figure 2, by switching switch 4 when necessary, CPU 1 can directly access the programs and memory of CPU 2, and CPU 1 can easily access CPU 2's programs and memory. You can perform backups.

Furthermore, CPUs 1 and 2 monitor each other,
When the CPU 2 is defective, the above-mentioned backup is performed, and when the CPU 1 is defective, the device is stopped by the CPU 2, so that serious accidents can be prevented from occurring.

Furthermore, in the present invention, since the addresses of the random access memories of the CPUs 1 and 2 are allocated as shown in FIG. 2, data transfer can be performed extremely easily and at high speed.

In other words, the address of CPU2 is "0000" ~
Although it is assigned only to "00FF" and "4100" to "7FFF", the address decoder 41 of CPU2
Since the upper two bits of address data A ₀ to _{A 15} are not decoded in , images of addresses "4100" to "7FFF" are formed at other addresses. Therefore, these addresses are
"0000" ~ "3FFF", "4000" ~ "7FFF",
"8000" to "BFFF" and "C000" to "FFFF" can be accessed equally.
Therefore, the addresses "6E00" to "6FFF" of the random access memory of CPU2 are "2E00" to "2FFF"
It can also be accessed at the address.

Therefore, in the above-mentioned circuit, by switching the switch 4 and directly connecting the random access memories 12 and 22, data can be transferred easily and at high speed.

Further, FIG. 3 shows a specific example of a configuration for data transfer.

In the figure, control buses 10c and 20c of CPUs 1 and 2, address buses 10a and 20a,
Data buses 10d and 20d are connected to switch 4 respectively.
c, 4a, and 4d. Also CPU
A normally on switch 30 is connected to the data bus 10d of
a is inserted, and this switch 30a and
It is connected to the CPU 1 through a normally off switch 30d.

Also, control bus 10c and address bus 1
The signal 0a is supplied to an address decoder 31 forming a part of the control means, and the signals from this decoder 31 are supplied to the chip select terminals of the read-only memory 11, random access memory 12, and IO port 13, respectively. Similarly, signals from the control bus 20c and the address bus 20a are supplied to the address decoder 41, and the signals from the decoder 41 are sent to the read-only memory 21 and the address bus 20a, respectively.
Random access memory 22 is supplied to the chip select terminal of the IO port. Note that the address decoder 41 is supplied with only the lower 14 bits A ₀ to A ₁₃ of the address bus 20a.

Further, the data transfer command signal from the decoder 31 is transmitted to the read/write control circuits 32 and 3.
3, and an address signal from address bus 10a is also supplied to control circuits 32 and 33. The signal from the control circuit 32 is supplied to the read/write control terminal of the random access memory 12, and the signal from the control circuit 33 is supplied to the control bus 10.
c.

Further, the switches 30a and 30b are switched by a data transfer command signal from the decoder 31.

Further, a command signal for data transfer from the decoder 31 is supplied to a control circuit 34 forming a part of the control means, and the signal from the control circuit 34 causes the switch 4 to be activated.
When c to 4d are turned on, this signal is sent to the CPU
The signal is supplied to the wait terminal of the CPU 1 through the bus request terminal of No. 2 and the AND circuit 35. Further, the bus acknowledge signal from the CPU 2 is inverted and supplied to the AND circuit 35.

Also, “4100” to “7FFF” from decoder 31
A signal indicating that the address has been designated is supplied to the control circuit 34.

In this circuit, when data is transferred, a signal from the decoder 31 is supplied to the control circuit 34 to turn on switches 4c to 4d, and a bus request is issued to the CPU 2 to
2 buses are made high impedance. Also, the switches 30a and 30b are switched to ground the data bus of the CPU 1.

Furthermore, when a bus acknowledge signal is output from the CPU 2 and the wait state of the CPU 1 is released, since all data buses are set to "0" in this CPU 1, the CPU 1 performs a so-called "NOP" process.

In this "NOP" processing, the value of the program counter is output to the address bus of CPU1, and for example, from "2E00", the value of the program counter is output for each processing.
The incremented addresses are provided to the random access memories 12,22. At the same time, this address is supplied to control circuits 32 and 33, and, for example, in the control circuit 32, a write control signal is formed when the address is in a predetermined range, and a read control signal is generated when the address is in another range, and is supplied to the random access memory 12. . Also control circuit 3
At step 3, a read control signal is generated when the address is in the above-mentioned predetermined range, and a write control signal is generated when the address is in another range, and is supplied to the random access memory 22 through the control buses 10c and 20c.

Therefore, in this circuit, addresses "2E00" to "2FFF" are supplied to the random access memories 12 and 22, and read/write control signals are supplied reciprocally to perform data transfer.

Further, when the transfer is completed and the value of the program counter reaches "3000", the output of the decoder 31 changes, the switches 4c to 4d, 30a, and 30b are switched to return to normal operation.

This is how data is transferred, and according to this circuit, data transfer is done with 1 "NOP"
Because it is performed for each process, extremely high-speed transfers are possible, making it possible to achieve transfers that are several times faster than traditional DMA processing.

Furthermore, since the CPU 1 continues to function, memory refresh is performed as usual even when dynamic type memory is used, for example. Therefore, unlike conventional DMA, there is no need to provide a special refresh circuit.

Furthermore, there is no need for a special IC for transfer, just adding a simple circuit such as a switch, and the circuit configuration is extremely simple.

Note that the processing of the CPU 1 during transfer may be other than "NOP" processing as long as it requires the shortest machine cycle and does not affect data transfer.

Also, by specifying the value of the program counter programmatically, data transfer can be set to "2E00".
It is also possible to start from any address between 2FFF and 2FFF. Therefore, by storing frequently needed data in rear addresses, the transfer time can be further shortened.

Furthermore, in this circuit, "4100" is set in CPU1.
~ When the address of "7FFF" is specified, the switches 4c to 4d are turned on in the control circuit 34,
CPU2 receives a bus request, and CPU1
Backup of CPU2 is performed. Furthermore, by providing an address for the IO port 24a, etc. of the CPU 2 within this address, the CPU 1 can directly control the IO port 24a, etc.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the present invention, FIG. 2 is a block diagram of an address, and FIG. 3 is a specific block diagram of main parts. 1 and 2 are CPUs, 4 is a switch, 11 and 21 are read-only memories, 12 and 22 are random access memories, and 14 is a control circuit.

Claims (1)

[Claims] 1: first and second central processing circuits; an input/output port circuit of the first central processing circuit; and storing data processed by the first and second central processing circuits. The first central processing circuit converts the data read from the input/output port circuit and stores it in the memory circuit, and the second central processing circuit converts the data read from the input/output port circuit and stores the converted data in the memory circuit. The converted data obtained through the circuit is processed and stored in the memory circuit, and the first central processing circuit converts the processed data obtained via the memory circuit into predetermined data. In a microcomputer that performs conversion processing and outputs the converted data through the input/output port circuit, the memory circuit comprises first and second random access memories, and the first and second random access memories The random access memory includes first address data output from the first central processing circuit and first address data output from the second central processing circuit.
and second address data different from the address data of the input/output port circuit and the first input/output port circuit. a first data bus shared by the random access memory and the first central processing circuit; a first data bus shared by the second random access memory and the second central processing circuit;
a second data bus shared by the central processing circuit; a first release means for releasing the first central processing circuit from the first data bus in response to a first control signal; a second release means for releasing said second central processing circuit from said second data bus in response to a control signal; and said first data bus, address bus and control bus in response to a third control signal. and a connection circuit that connects the second data bus, the address bus, and the control bus; and a control circuit that outputs the first, second, and third control signals in response to signals from the second central processing circuit. means for connecting the first and second data buses, the address bus, and the control bus, and disconnecting the first and second central processing circuits from the first and second data buses; , the converted data and the arithmetic processed data are transferred between the memory areas of the first and second random access memories under the control of the second central processing circuit; Features of microcomputer.