JPH04604Y2 - - Google Patents

Description

[Detailed Description of the Invention] (Industrial Field of Application) The present invention relates to a circuit for counting errors in a transmission line and for generating and transmitting an alarm.

(Prior Art) Conventionally, in circuits that count error pulses and generate and send out error alarms, the phenomenon of counting more than a set number (K) of error pulses in a certain period of time T occurs.
A system was adopted in which an alarm would be generated and sent out if the alarm occurred twice in a row. Here, T, K, and N were each determined by the error occurrence probability of the transmission path.

The error alarm generation/sending circuit according to the prior art includes a timer circuit, an error counting circuit, an N-stage shift register, and an AND circuit. The timer circuit is
Pulses are generated at a constant period T. When the error counting circuit inputs an error pulse and counts K or more error pulses, the output state changes from a low level to a high level, and this state is maintained until a pulse is input from the timer circuit. It changes to a low level by a pulse from The N-stage shift register stores the state of the output of the error counting circuit as the Q output of each stage of flip-flops when the outputs of the timer circuit and error counting circuit are input to the clock input terminal and data input terminal, respectively. be. The AND circuit calculates the AND of the Q outputs of the flip-flops at each stage of the N-stage shift register. Q of each stage flip-flop
When all the outputs become high level, that is, when the output of the error count signal becomes high level N times in a row, an error alarm is generated and sent.

(Problems to be Solved by the Invention) In the error alarm generation and transmission circuit according to the prior art, the logical sum of the Q outputs of the flip-flops in each stage of the N-stage shift register is calculated in order to generate and transmit the alarm. When N becomes large, multi-input
There was a problem that an AND gate or NAND gate was required. Furthermore, AND gate,
Alternatively, if there is a limit to the number of NAND gate inputs, several gates are required, resulting in a complicated circuit configuration and an increase in size.

The purpose of the present invention is to eliminate the above drawbacks by providing an alarm generation/sending function in addition to the function of storing the output of the error counting circuit in an N-stage shift register, and to achieve economical efficiency with a simple configuration. An object of the present invention is to provide a good error alarm generation and transmission circuit.

(Means for Solving the Problems) The error alarm generation/sending circuit according to the present invention includes a timer circuit, an error counting circuit, a shift register, and an inverting circuit.

The timer circuit is for generating clock pulses at regular intervals.

The error counting circuit can be set to an initial state by the clock pulse of the timer circuit, and changes its output state when error pulses are input and a predetermined number or more of error pulses are counted.

The shift register inputs the clock pulse output from the timer circuit and the data output from the error counter circuit to the clock input terminal and data input terminal, respectively, and shifts the data using a multi-stage flip-flop to output an alarm. It is.

The inversion circuit calculates the inversion of the logical sum or logical product between the data output of the error counting circuit and the Q output of the first stage flip-flop of the shift register, and supplies the result to the reset terminal or set terminal of the shift register. .

(Example) Next, a false alarm generation and transmission circuit according to the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a false alarm generation and transmission circuit according to the present invention. In FIG. 1, 1 is an error counting circuit, 2 is a timer circuit, 3 is an OR circuit for a pair of input signals or an inverting circuit for calculating a logical product, and 4 is an N-stage shift register. In the shift register 4, D ₁ and Q ₁ represent the data input terminal and Q output terminal of the first stage flip-flop, respectively, and Qn represents the Q output terminal of the nth stage flip-flop. C
represents the clock input terminal of the flip-flop in each stage, and RESET/SET represents the reset terminal and set terminal of the flip-flop in each stage, respectively.

First, when the error counting circuit counts K or more error pulses and becomes high level, an OR circuit is used for the inverting circuit 3, and the output of the error counting circuit 1 and one stage of the N-stage shift register 4 are used. The logical OR with the output _Q1 of the second flip-flop is calculated and inputted to the reset terminal of the N-stage shift register 4. If the output of the error counting circuit 1 becomes high level before the pulse is sent out from the timer circuit 2, the state of the output of the error counting circuit 1 is changed to the state of the output of the error counting circuit 1 in the N-stage shift register 4 when the pulse is sent out from the timer circuit 2. It is stored as the _Q1 output of the first stage flip-flop, and at the same time the output of the error counting circuit 1 becomes low level. When the output of the error counter circuit 1 is at a high level N times in a row before a pulse is sent from the timer circuit 2, the output Qn of the N-th stage flip-flop of the N-stage shift register 4 becomes a high level. .

The output of this Nth stage flip-flop can be used as an error alarm. When a pulse is sent from timer circuit 2, the error count signal becomes low level,
In this state, when the next pulse from the timer circuit 2 is sent out, the OR output becomes a low level, and the output Q of the flip-flop in each stage of the N-stage shift register 4 becomes a low level. becomes the initial state.

Second, when the error counting circuit 1 counts K or more error pulses, an AND inverting circuit is used as the inverting circuit 3 when changing from a high level to a low level, and the output of the error counting circuit 1 and N Output of the first stage flip-flop of stage flip-flop 4
The inversion of the AND with Q ₁ is performed in N-stage shift register 4.
input to the set terminal of As a result, when the output of the error counting circuit 1 is at a low level, the set terminal input is stored as the output of the flip-flop of each stage of the N-stage shift register 4, and if the output is repeated N times consecutively, the input of the set terminal is stored as the output of the flip-flop of the Nth stage. Since the output changes from high level to low level, this output can be used as an alarm.

FIG. 2 is a circuit diagram using a four-stage shift register showing in detail the embodiment of the present invention shown in FIG. In Figure 2, 5 to 12 represent flip-flops, and 13 and 14 represent NOR flip-flops, respectively.
Represents a gate. If an error pulse is input before the pulse is output from the timer circuit 2, the output Q of each of flip-flops 5 to 8 is
The terminals become high level one after another. Therefore, if four or more error pulses are input, the flip-flop 8
The Q output of NOR gate 14 becomes high level, and the output of flip-flops 9 to 1 becomes high level.
A four-stage shift register 4 consisting of 2 is set. When a pulse is output from the timer circuit 2 in this state, the output Q of the flip-flop 9
becomes a high level, and at the same time, the Q output of the four-stage shift register 4 consisting of flip-flops 5 to 8, which are counting error pulses, becomes a low level. If four or more error pulses are input before the pulse is output from the timer circuit 2, the flip-flop 8
The state of the output of is stored as the Q output of flip-flops 9-12. If four or more error pulses are input before the pulses are output from the timer circuit 2 four times in a row, the flip-flop 1
The Q output of 2 becomes high level. This output can be used as an alarm output.

When a pulse is output from the timer circuit 2 under the condition that the output Q of the flip-flop 8 is at a low level, the output Q of the flip-flop 9 becomes a low level, and the output of the NOR gate 14 that constitutes the inverting circuit 3 becomes a low level. Become. Therefore, the outputs Q of flip-flops 9 to 12 become low level. In other words,
In this embodiment, when the phenomenon of counting four or more erroneous pulses occurs four times in a row during a certain period of time T, the alarm output changes from a low level to a high level.

(Effects of the invention) As explained above, according to the invention, in addition to the function of storing the output of the error counting circuit, it also has the function of generating and sending an alarm to the N-stage shift register, thereby increasing the number of stages. Even if the number of flip-flops increases, there is no need to calculate the AND of multiple inputs, and the effect is that the circuit can be simplified and economical efficiency can be improved.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a false alarm generation and transmission circuit according to the present invention. Figure 2 shows
FIG. 2 is a circuit diagram showing details of the error alarm generation/sending circuit of FIG. 1; 1...Error counting circuit, 2...Timer circuit, 3...
...Inverting circuit, 4...Shift register, 5-12...
...Flip-flop, 13, 14...NOR gate.

Claims (1)

[Scope of utility model registration request] The initial state can be set using a timer circuit that generates clock pulses at a constant cycle and the clock pulses of the timer circuit, and the output state changes when error pulses are input and a predetermined number or more of error pulses are counted. The clock pulse outputted from the timer circuit and the data outputted from the error counting circuit are inputted to a clock input terminal and a data input terminal, respectively, and the data is shifted by a plurality of flip-flops to generate an alarm. A shift register for outputting the error counter circuit, and a logical sum or inversion of the logical product between the data output of the error counting circuit and the Q output of the first stage flip-flop of the shift register, and a reset terminal or a set terminal of the shift register. What is claimed is: 1. An error alarm generation/sending circuit comprising: an inverting circuit for supplying a false alarm;