JPH0460773A - Layout verifying device - Google Patents

Abstract

PURPOSE:To reduce pseudo errors in the verification of a layout by shorting and removing information on a non-extracted element form connection information before collation is executed. CONSTITUTION:A layout verifying device 10 inputs first connection information 13 being the reference of layout generation in a circuit element and second connection information 14 extracted from layout information so as to collate them. A processing part 11 removes information on the non-extracted element which cannot be extracted by a method obtaining second connection information 14 from layout information from first connection information 13 and generates third connection information. A collation part 12 collates generated third connection information with second connection information 14 and outputs a collation result 17. The processing part 11 generates third connection information 16 based on control information 15 including non-extracted element information which is separately inputted and connection information on a circuit after the non-extracted element is removed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is applied to a layout verification device that performs layout verification in the design of LSI and the like.

〔overview〕

The present invention provides a layout verification device that collates connection information (1) that is a reference for creating a layout of circuit elements with connection information (II) extracted from the layout information. The occurrence of pseudo errors is reduced by removing information about non-extracted elements that cannot be extracted from the connection information (III) and then comparing it with the connection information (II).

[Conventional technology]

Conventionally, in this type of layout verification device, when extracting connection information from layout information such as LS■, due to limitations in graphical calculation processing, a resistor element made of polycrystalline silicon wiring or a resistor composed of a depletion type MO3FET was used. There is a problem in that the element is recognized as a general wiring, making it difficult to extract it as a resistive element. Therefore, special data has been created on the layout to help recognize the resistive elements.

[Problem to be solved by the invention]

In the conventional layout verification device described above, when extracting connection information from the layout information of LSI etc., due to the limitations of graphical calculation processing, it is difficult to use a resistance element made of polycrystalline silicon wiring or a resistance element composed of a depletion type MO3FET. , it was recognized as a general wiring, and it was difficult to extract it as a resistance element. As a result, since the connection information extracted from the layout information lacks information on the resistive elements, a pseudo error will be output when compared with the connection information that was the basis for creating the layout.

Generally, layout verification equipment outputs a large number of error messages in response to verification results, but the task of classifying true errors and pseudo errors from among them is done manually, and a large amount of man-hours are spent on the classification work. , there is also the risk of missing a true error. To this end, the layout verification device is required to reduce pseudo error output as much as possible.

One way to avoid this is to create special data on the layout that allows the resistor elements to be recognized using graphical calculations, but this poses problems in terms of man-hours and reliability.

The purpose of the present invention is to solve the above-mentioned problems.
An object of the present invention is to provide a layout verification device that reduces the occurrence of pseudo errors.

[Indispensable means to solve problems]

The present invention provides layout verification that includes a means for inputting and comparing first connection information (III) that is a reference for creating a layout of circuit elements and second connection information (II) extracted from the layout information. In the apparatus, a process of generating third connection information (III) in which information regarding non-extracted elements that cannot be extracted by the method of obtaining second connection information (II) from layout information is removed from the first connection information (1). and a collation means for collating the generated third connection information (DI) with the second connection information (I[) and outputting a collation result.

Further, in the present invention, the processing means generates the third connection information (
III).

[Effect]

Prior to the collation process in layout verification, the processing means deletes information about elements that cannot be recognized by graphical operations input separately from the connection information (III) that is the basis for layout creation, and outputs the information as connection information (III). do. Then, the collation means collates this connection information (III) with the connection information (II) and outputs the collation result.

Therefore, the occurrence of pseudo errors related to non-extracted elements is eliminated, and the occurrence of pseudo errors can be reduced.

〔Example〕

Hereinafter, embodiments of the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

The layout verification device 10 of this embodiment uses first connection information (IO2,
Second connection information ([)14 extracted from layout information
In a layout verification device equipped with a means for inputting and verifying, the present invention is characterized in that the relevant Based on control information 15 input from the outside including non-extracted element information and connection information of the circuit after removing the non-extracted element, the input connection information (the third one from which information regarding the non-extracted elements has been removed from IO2) is inputted from the outside. Comprising a processing unit 11 as a processing means for generating connection information (III) 16, and a collation unit 12 for collating the generated connection information (III) 16 and connection information (IrO2) and outputting a collation result 17. There is.

Next, the operation of the second embodiment will be explained.

The processing unit 11 processes the connection information (III) according to the control information 15.
) 13 (non-extracted elements) is short-circuited and connection information (III) 16 is output. Verification B12 is
The connection information (III) 16 output from the processing unit 11 is compared with the connection information ([04), and a comparison result 17 is output.

Next, the operation of the processing section 11 will be explained using a specific example.

The circuit diagram image shown in Figure 2 is the connection information (III) 1
3 in the format shown in FIG. In Figure 3, NET1, NET2, NET4 and N E
T5 is the net, NVI and NV2 are the inverters,
R is the resistor, 21.23 and 25 are pins A, and 2
2.24 and 26 are pins Y. Now, the connection information (
Connection information (
II) Suppose that when drawing 14, the resistance R cannot be recognized due to limitations such as graphical calculations and is regarded as a wiring.

As a result, the connection information (I[) 14 becomes the circuit diagram image shown in FIG. 4, and is given in the format shown in FIG. 5. If the connection information (1) 13 in FIG. 3 is compared with the connection information (II) 14 in FIG. 5 in this state, a pseudo error will be output because the resistance R does not exist in the connection information (II) 14.

Now, assume that a short circuit removal designation for the resistor R is input to the processing unit 11 in the format shown in FIG. Here, the designation order 31 is an identifier representing the designation of short circuit removal. Further, the designation order 32 designates an element that shortens short-circuit removal, which is the resistor R in this example. Specified order 33 is to connect pin Y22 of inverter NVI and pin A of inverter NV2 after removing resistor R.
Specify the net name to connect 25, in this example NET3
It is.

The processing unit 11 outputs the connection information (III) 16 shown in FIG. 7 by deleting the description regarding the resistor R from the connection information (IO2 in FIG. 3) and replacing the name of the net connected to the resistor R with NET3. do.

It is clearly seen that this has connection information equivalent to the connection information (II) 14 in FIG. 5. Therefore, a pseudo error regarding the resistance R does not occur during verification. 8th
The figure shows a circuit diagram image of the connection information (III) 16.

Next, a second embodiment of the present invention will be described.

The basic configuration of the second embodiment is the same as that of the first embodiment shown in FIG. 1, but the format of the input control information 16 is different, and the processing of the processing unit 11 is correspondingly different.

FIG. 9 is an explanatory diagram showing the control information 15 given to the processing section 11 in the second embodiment. The difference from the first embodiment shown in FIG. 6 is that after removing the resistor R, the pin Y22 of the inverter NVI and the pin A25 of the inverter NV2 are
This is an example of designation in which the name of the net connected to pin A of resistor R is used as the name of the net connecting . The designation order 42 corresponds to that designation. Note that the designation order 41 is an identifier indicating the designation of short circuit removal.

The connection information (III) 16 after processing is shown in FIG.
The figure shows the circuit diagram image.

〔Effect of the invention〕

As described above, the present invention has the effect of reducing pseudo errors in layout verification by short-circuiting and removing information regarding non-extracted elements from connection information (III) before performing verification.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram showing a circuit diagram image of the connection information (III). FIG. 3 is a diagram showing an example of the format of the connection information (III). FIG. 4 is a diagram showing a circuit diagram image of the connection information (II). FIG. 5 is a diagram showing an example of the format of the connection information (II). FIG. 6 is a diagram showing an example of the format of the control information. FIG. 7 is a diagram showing an example of the format of the connection information (I[I). FIG. 8 is a diagram showing a circuit diagram image of the connection information (DI). FIG. 9 is a diagram showing an example of the format of control information in the second embodiment of the present invention. FIG. 10 is a diagram showing an example of the format of the connection information (III). FIG. 11 is a diagram showing a circuit diagram image of the connection information (1). lO...Layout verification device, 11...Processing unit, 1
2... Verification unit, 13... Connection information (r), 14...
- Connection information (II), 15... Control information, 16...
Connection information (Itl), 17... Verification result, 21.23
．． 25...Pin A, 22.24.26...Pin ¥1
31.32.33.41.42--Specified item, NETI
~NET5...net, NVI, NV2...inverter, R...resistance.

Claims (1)

[Claims] 1. Means for inputting and comparing the first connection information (I) that is the basis for creating the layout of circuit elements and the second connection information (II) extracted from the layout information. third connection information (III) in which information about non-extracted elements that cannot be extracted by the method of obtaining the second connection information (II) from the layout information is removed from the first connection information (I); A layout characterized by comprising a processing means for generating the generated third connection information (III) and the second connection information (II) and a collation means for outputting a collation result. Verification device. 2. The processing means includes means for generating the third connection information (III) based on control information including separately input non-extracted element information and circuit connection information after removing the non-extracted elements. A layout verification device according to claim 1.