JPH0460831A - Data processor - Google Patents

Abstract

PURPOSE:To easily handle a data arranging bytes in both a Big-Endian form and a Little-Endian form by providing a means to discriminate the byte arrangement of a multibyte length data and to output a byte arrangement instructing signal, and a multibyte length calculation logic computing element to select a digit carrying / borrowing signal from a signal outputted from a high-order or low-order computing element. CONSTITUTION:The output of a register is connected to a multibyte length calculation logic computing element 3 without changing the arrangement of bytes. The multibyte length calculation logic computing element is composed of low-level ALU 30 for the unit of a byte. Carrying bits outputted form the respective low-level ALU are transmitted to the low-level ALU of the adjacent byte. The input carry to the low-level ALU is inputted from the carry of the adjacent byte after being selected to low-order byte/high-order byte or high-order byt/low-order byte according to the byte arrangement instructing signal. Thus, while supporting the byte arrangement both in the Big-Endian and Little-Endian forms and avoiding load in the case of access, the byte arrangement in both forms can be easily handled.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology and Problems to be Solved by the Invention Means for Solving the Problems Effects of the Invention [Summary] Regarding the method of processing data with different byte orders in a data processing device configured to perform all operations between a storage device and a register file, such as an instruction reduction type data processing device, multi-byte length Ascending order (Big
-Endian) format, and descending order (Litt
While supporting the byte arrangement of the image format (LeEndian) format, it avoids the load when accessing the main memory, and
The purpose of this invention is to provide a data processing device that can easily handle byte-aligned data in an image format, and means for determining the byte alignment of multi-byte long data placed in the register file and outputting a byte alignment instruction signal. and carry 7 input to the arithmetic logic unit (ALU) configured in byte units.
The digit down signal is changed to the upper position by the above-mentioned byte arrangement instruction signal ■.

Alternatively, it is configured to have a multi-byte length arithmetic logic unit (multi-byte length ALU) that selects from signals output from lower-order calculation units. In addition, for arithmetic units (shifters, etc.) other than the multi-byte length arithmetic and logic unit (multi-byte length AL[l), a byte order converter (M
IX). In addition, for arithmetic units (multipliers, etc.) other than the above-mentioned multi-byte length arithmetic and logic unit (multi-byte length ^LU), there are two types of bytes and two corresponding types of arithmetic units, and the above-mentioned byte arrangement instruction is provided. Based on the signal
It is configured to have means (selector) for selecting the outputs of the two types of arithmetic units.

[Industrial application field]

The present invention provides a data processing device configured such that main memory access is performed between the main memory device and a register file, and all operations are performed between the register files, such as an instruction reduction type data processing device, in which byte sequences are different. Concerning methods of processing data.

Traditionally, in byte addressing type computers, when accessing multi-byte length data stored in main memory, a (Big-Endian) format is used in which the upper byte of the data corresponds to the byte data at the lower address of the main memory. Conversely, the lower byte of multi-byte data corresponds to the lower address of the main memory (LittleJnd).
ian) format.

In the past, computers handled only one of these formats, but today, when there are many opportunities for data exchange between different models, it is necessary to handle both image formats. For this reason, some recent processors are equipped with the ability to handle this image format.
Its functionality is not sufficient, and it is required to be able to easily switch between image formats.

[Prior art and problems to be solved by the invention] Fig. 2 is a diagram illustrating a conventional data processing device that handles byte arrangement, where (al) and (a2) show different byte arrangement formats, and ( b) shows a conventional method for handling two types of byte arrangements.

As mentioned above, in a byte-addressing computer, when accessing multi-byte length data stored in main memory, the upper byte of the data is Correlate with the byte data at the lower address of memory (Big-Endian) (ascending order)
One uses the format (see figure (al)), and the other uses the Little-Indian (descending order) format (see figure (a2)), in which the lower byte of multi-byte data corresponds to the lower address of the main memory. There is.

=6 In conventional processors, in order to handle the byte arrangement of the image format as described above, as shown in FIG. or between the arithmetic unit 3 and the main storage device 1,
A byte sequence converter 6 is provided to convert the byte sequence during data transfer.

However, due to the speed gap with the main memory device 1 that occurs as processor speeds increase, the load of converting the byte order during data transfer cannot be ignored, and this conversion process is one of the factors that prevent processors from increasing speed. It has become.

Furthermore, with conventional devices, it is necessary to know in advance the byte arrangement of the data to be imported when loading data. Therefore, in cases where different data sequences coexist in the main memory 1, the multi-byte length data cannot be accessed unless information indicating which data sequence is included in advance. Therefore, there was a software problem.

Information indicating the arrangement of the byte data may be placed, for example, at the beginning or end of a series of data on the main memory.

Therefore, when accessing data with such a structure in main memory and accessing multi-byte long data before or at the same time as the information indicating the data arrangement, the data taken into register 2 may be different from the arrangement of the computing units 3, and the imported data must be loaded again by program procedure, etc.
I had to convert it.

In view of the above-mentioned conventional drawbacks, the present invention has been developed to
Endian (ascending order), Little4ndian
It is an object of the present invention to provide a data processing device that can easily handle the byte arrangement of the image format while supporting the byte arrangement of the image format (descending order), while avoiding the load when accessing the main memory.

[Means to solve the problem]

The above problems are solved by a data processing device configured as follows.

(1) It is a so-called instruction reduction type data processing device configured such that main memory access is performed between the main memory and a register file, and all operations are performed between the register files. means for determining the byte arrangement of the multi-byte length data and outputting a byte arrangement instruction signal (■);

Multi-byte length in which the carry and 7-digit down signals input to the arithmetic logic unit (ALU) configured in bytes are selected from the signals output from the upper or lower arithmetic unit by the byte arrangement instruction signal ■. Arithmetic logic unit (multi-byte length A
LU).

(2) In the data processing device, for an arithmetic unit other than the multi-byte arithmetic and logic unit (multi-byte ALU), for example, a byte order converter (MUX) between the register file and the thick; Configure it to have .

(3) In the above data processing device, two types of bytes and two corresponding types of multipliers 1 are provided for an arithmetic unit other than the multi-byte length arithmetic logic unit (multi-byte length ALU), for example, a multiplier. , 2, and the two types of multipliers 1 . Alternatively, the configuration is such that means (selector) for selecting two outputs is provided.

(4) In the data processing apparatus of items 1 to 3 above, the byte alignment information for generating the byte alignment instruction signal (2) is configured to be included in an internal register or an operation instruction code of the data processing apparatus.

(5) In the data processing device described in Items 1 to 5 above, an intermediate register not described in the operation instruction is provided in the register file, and between the intermediate registers,
It is configured to perform the calculation described in 3.

[Effect]

That is, according to the present invention, in a data processing device configured such that main memory access is performed between the main memory device and a register file and all operations are performed between the register files, for example, an instruction reduction type data processing device, The output of the register is a multi-byte length arithmetic logic unit (LU to multi-byte length)
is connected without changing the byte order.

The multi-byte length arithmetic logic unit (multi-byte length ALU) is
It is composed of a low-level ALU in units of bytes. The carry (carry up, 7 carry down/shift out) bits output by each low level ALU are sent to the low level ALU of the adjacent byte.

The input carry to the low level ALU is selected from the carry of the adjacent byte, from the lower byte to the upper byte, or from the upper byte to the lower byte, according to the byte arrangement instruction signal (2).

As a result, whether the high-order byte of the numerical value is stored in the high-order side of the register or the low-order side,
It becomes possible to perform arithmetic and logical operations without being aware of the byte arrangement.

Alternatively, two types of arithmetic units corresponding to the arrangement of bytes, for example, multipliers 1.2, are provided, and the two multipliers 1.2 are provided. Or, from the result of 2, based on the byte alignment instruction signal,
Select one and output it.

In addition, a byte order converter (MIX) is provided between the register file and the arithmetic unit 1, for example, thick, and after converting the byte order based on the above-mentioned byte order instruction signal (■), the shifter performs a shift operation. , and then converts it to the original byte order and outputs the shift result.

Therefore, in the data processing device of the present invention, the load on main memory access is reduced because the data arrangement is not converted when transferring data from the main memory to the register.

In addition, since it is not necessary to know which data arrangement the data is in when loading data into the arithmetic unit, it is possible to easily handle data in which image formats are mixed.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention, in which (a) shows an example of the configuration of a multi-byte length arithmetic logic unit (multi-byte length ALU), and (b) shows an example of the system configuration. ing.

In the present invention, data is transferred to the register file 2 without being aware of the byte arrangement, and the arithmetic unit,
For example, a multi-byte length arithmetic logic unit (multi-byte length ALU)
) When performing arithmetic and logical operations in step 3, the multi-byte length arithmetic and logic unit (multibyte length ALU) 3 is configured with a byte-based low-level arithmetic and logic unit (ALtl) 30, and the byte order is instructed. For example, the direction of propagation of the carry signal from the low-level arithmetic and logic unit (^LU) 30 for each byte can be controlled by the signal ■, or two types of arithmetic units, such as multipliers, corresponding to the byte can be provided. Then, the calculation results of the two multipliers 1 and 2 are selected by the signal (■) instructing the byte arrangement, or byte arrangement conversion is performed between the register file 2 and the arithmetic unit, for example, the shifter 50. Means for converting the byte arrangement of input/output data to the shifter 50 by providing MIX devices (MIX) 51 and 52 and converting the byte arrangement of input/output data to the shifter 50 by the above-mentioned byte arrangement instruction signal (2) is a means necessary for carrying out the present invention.

Note that the same reference numerals indicate the same objects throughout the figures.

Hereinafter, with reference to FIG. 1, a data processing method corresponding to the difference in byte arrangement in the data processing apparatus of the present invention will be explained.

FIG. 1(a) shows an example of the configuration of a multi-byte arithmetic and logic operation circuit according to the present invention, and shows an example of a data processing device in which the register and data bus are 4 bytes long.

In the example shown in the figure, the main storage device 1 and the register file 2 are directly connected, but a cache memory may be provided between the main storage device 1 and the register file 2.

The present invention provides a data processing device configured such that main memory access is performed between the main memory device l and the register file 2, and all operations are performed between the register file 2, such as an instruction reduction type data processing device. Applies to equipment.

First, as shown in figure (b), when loading data from main memory l to register file 2, the addressed byte is loaded to the upper byte side of the register, regardless of the byte arrangement of the data. .

The multi-byte length arithmetic and logic unit 3 is a byte-based low-level arithmetic and logic unit (hereinafter referred to as AL
In this embodiment, it is shown that it is composed of four low-level ALUs 30. Each low-level ALU 30 corresponds to a byte position of a register, and during an operation, bytes of the same byte position of the source registers 1 and 220 are input to the same low-level ALU 30.

A byte arrangement instruction signal ■ is input to the ALU 30,
This controls the propagation direction of the carry signal between the low level ALUs 30.

In this figure, Sol, S02 is the multi-byte length ALU
3, and Sll and S12 indicate the carry output to the multi-byte length ALU 3. Also, the signal line ■ connecting each low level ALU30 is
This is a carry propagation path, and the carry signal is propagated from the upper byte to the lower byte or from the lower byte to the upper byte in the selector (SEL) 31 in accordance with the above-mentioned byte arrangement instruction signal (2).

As shown in FIG. 1(b), there are two types of multipliers, 1. 240.41
There is a byte arrangement instruction signal ■, selector 42
function so that its output is selected.

The shifter 50 also shifts an arbitrary number of bits from 1 bit to 32 bits at a time (left shift).

, right shift, or circular shift). In byte arrangement converters (MUX) 51 and 52 provided before and after the shifter 50, the byte arrangement is converted in accordance with the byte arrangement instruction signal ■.

That is, in accordance with the byte arrangement instruction signal (2), the byte arrangement of the shifter 50 is converted into a corresponding byte arrangement in the byte arrangement converter (MIX) 51, and then a shift operation is performed, and the shifted result is converted into a byte arrangement converter (MIX) 51. Vessel (M
UX) At 52, the above byte arrangement instruction signal ■
is converted to the original byte order.

The means for generating the above-mentioned byte arrangement instruction signal (2) will be explained below.

As mentioned above, if the byte arrangement information is placed at the beginning or end of a series of data strings stored in the main memory 1, the program does not know the structure of the data string. Therefore, the program means stores the byte order information, for example, in a specific register of the register file 2 or in the dedicated flag register 21 (FIG. 1(a)
)), it is possible to generate the byte arrangement instruction signal (2).

Furthermore, by including the byte order information in the code of various arithmetic instructions, the byte order instruction signal ■ can be outputted at the time when the arithmetic instruction is set in an instruction register (not shown). I can do it.

In addition, in the above embodiment, an example was explained in which the byte alignment processing is performed for the operation between the register files 2, but
For example, for instructions between memories, between memory registers, etc., an intermediary register 20 that is not described in the code of the operation instruction is provided in the register file 2, and between the memories, between memory registers, etc. By configuring the above-mentioned byte and corresponding processing to be executed via the intermediary register 20 when an instruction is detected, the present invention can also be applied to instructions between memories, between memory registers, etc. operations can be provided.

In this way, the present invention transfers data to the register file 2 without being aware of the byte arrangement, and also transfers data to the register file 2 without being aware of the byte arrangement.
When performing arithmetic and logical operations on the multi-byte length arithmetic and logic unit (LU) 3, the multi-byte length arithmetic and logic unit (multi-byte length ALU) 3 is configured with a low-level arithmetic and logic unit (ALU) 30 in units of bytes, and the byte arrangement is For example, the low-level arithmetic and logic unit (^LU) for each byte is activated by the instructing signal ■.
To control the propagation direction of the carry signal from 0, two types of arithmetic units, for example, multipliers, corresponding to the bytes are provided, and the two multipliers 1. Selecting the calculation result in 240.41 with the signal ■ that instructs the byte arrangement,
Alternatively, a byte order converter (MIIX) 51.5 is installed between the register file 2 and the arithmetic unit, for example, the chic 500.
2 is provided, and by the above-mentioned byte arrangement instruction signal ■,
The feature is that the byte arrangement of input/output data to the thick 50 is converted.

〔Effect of the invention〕

As described above in detail, the data processing device of the present invention is a data processing device configured such that main memory access is performed between the main memory device and the register file, and all operations are performed between the register files. , an instruction reduction type data processing device includes means for determining the byte arrangement of multi-byte long data placed in the register file and outputting a byte arrangement instruction signal ■, and an arithmetic logic unit (ALU) configured in byte units. ), the carry and 7 digit down signals are input to the upper byte arrangement instruction signal.

Alternatively, it is configured to have a multi-byte length arithmetic and logic unit (multi-byte length ^LU) that selects from signals output from a lower-order arithmetic unit (ALU). Furthermore, a byte order converter (MUX) is provided between the register file and the arithmetic units for arithmetic units (shifters, etc.) other than the multi-byte arithmetic and logic unit (multi-byte ALU). In addition, for arithmetic units (multipliers, etc.) other than the above-mentioned multi-byte length arithmetic and logic unit (multi-byte length ALU), two types of bytes and two corresponding types of arithmetic units (multipliers 1 and 2) are provided. However, since it has a means (selector) for selecting the output of the two types of arithmetic units based on the above-mentioned byte arrangement instruction signal (■), it is necessary to be aware of the byte arrangement when loading data into the register. This has the effect of making it possible to load the information into the arithmetic unit without any problems, thereby greatly contributing to improving the performance of such computer systems.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention. FIG. 2 is a diagram illustrating a conventional data processing device that handles byte alignment. It is. In the drawing, ■ is the main storage device. 2 is a register file or register. 3 is a multi-byte length arithmetic logic unit (multi-byte length ALU)
. 30 is an arithmetic logic unit (ALU) in units of bytes. 40 is a multiplier 1. 41 is a multiplier 2, 42 is a selector, and 50 is a shifter. 51.52 is a byte alignment converter (MIX). 6 is a byte order converter. ■ is a byte alignment instruction signal. are shown respectively. Figure 1 (Part 1) Figure (Part 2) A diagram explaining a conventional data processing device that handles byte sequences

Claims (5)

[Claims] (1) A data processing device configured such that main memory access is performed between the main memory device (1) and a register file (2), and all operations are performed between the register file (2), the register file The byte arrangement of the multi-byte length data placed in (2) is determined, and the byte arrangement instruction signal ([1]
) and a carry/logic unit (21) for outputting
The carry down signal is sent to the upper or lower arithmetic logic unit (ALU) (
30) A data processing device characterized by having a multi-byte length arithmetic and logic unit (multi-byte length ALU) (3) that selects from the output signal. (2) In the above data processing device, the register file (2) and the arithmetic unit (5) are connected to the multi-byte length arithmetic logic unit (multi-byte length ALU) (3).
A data processing device characterized by having a byte order converter (MUX) (51, 52) between 0) and 0). (3) In the above data processing device, two types of bytes and two corresponding types of arithmetic units (40, 41) and the above-mentioned byte arrangement instruction signal (
[1]) Based on the above two types of arithmetic units (40, 41)
A data processing device comprising means (selector) (42) for selecting an output of. (4) In the data processing device according to any one of claims 1 to 3, the byte order information for generating the byte order instruction signal ([1]) is stored in an internal register (21) of the data processing device or in an arithmetic instruction code. A data processing device characterized by having: (5) In the data processing device according to any one of claims 1 to 5, the register file (2) is provided with an intermediary register (20) that is not described in the operation instruction, and the intermediary register (20) is provided in the register file (2).
20) A data processing device characterized in that the calculations according to claims 1 to 3 are performed.