JPH0461068U

JPH0461068U -

Info

Publication number: JPH0461068U
Application number: JP10395590U
Authority: JP
Priority date: 1990-10-01
Filing date: 1990-10-01
Publication date: 1992-05-26

Description

[Brief explanation of drawings]

第１図は本考案の一実施例のブロツク図、第２
図は本考案によるサンプリング・タイミングを示
す図、第３図は従来のサンプリング・タイミング
を示す図である。１……サンプリング制御装置、２……トリガ設
定装置、３……入力端子設定装置、４……サンプ
リング信号出力装置、５……データ取込装置、６
……表示装置、７……データメモリ、１１……サ
ンプリング回数出力回路、１２−１〜１２−ｎ…
…回数比較回路、１３−１〜１３−ｎ……周期変
更タイミング設定回路、１４−１〜１４ｎ……周
期設定回路。 Figure 1 is a block diagram of one embodiment of the present invention;
The figure shows the sampling timing according to the present invention, and FIG. 3 shows the conventional sampling timing. DESCRIPTION OF SYMBOLS 1... Sampling control device, 2... Trigger setting device, 3... Input terminal setting device, 4... Sampling signal output device, 5... Data acquisition device, 6
...Display device, 7...Data memory, 11...Sampling number output circuit, 12-1 to 12-n...
...Number of times comparison circuit, 13-1 to 13-n... Cycle change timing setting circuit, 14-1 to 14n... Cycle setting circuit.

Claims

[Scope of utility model registration request]

In a logic analyzer that samples and stores input data and displays it visually, there is a plurality of cycle setting means for setting the cycle of sampling timing of input data, and a cycle change timing corresponding to each of the plurality of cycle setting means. A plurality of period change timing setting means for setting the number of times of the designated sampling timing, and counting the number of occurrences of the sampling timing to determine whether the sampling timing matches the number of times set in each of the plurality of period change timing setting means. A logic analyzer comprising sampling frequency detection means that activates the corresponding cycle setting means when detected, and sets a plurality of types of sampling timing cycles in one measurement.