JPH0461314A - Method for forming pattern on semiconductor wafer - Google Patents

Abstract

PURPOSE:To reduce the stress produced in a base film by performing exposure, development, and etching to dicing lines only and, after the photosensitive resist used for the dicing lines is removed, exposing and developing a circuit pattern after another photosensitive resist is applied. CONSTITUTION:After only dicing lines 4 are patterned, the resist used for the lines 4 is removed. As a result, the stress produced in a base film 3 can be dissipated, because the film 4 containing the stress is divided into small areas by the dicing lines 4. Then the second resist is applied and circuit patterning is performed. When the stress produced in the base film 3 is large, the second resist tends to be peeled off. When the dicing lines 4 are formed first, etching in the lateral direction can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for forming patterns on semiconductor wafers (hereinafter referred to as wafers), and is used in the field of manufacturing electronic materials, for example.

Used for forming circuit patterns on wafers, etc.

[Conventional technology]

Figure Wc6 is a top view of a wafer showing a conventional wafer pattern forming method. As shown in the figure, dicing lines (4) and circuit patterns (5) are simultaneously formed inside the wafer (1).

[Problem a that the invention seeks to solve]

Since conventional wafer pattern formation methods are performed in one or more ways, dicing lines and circuit patterns are formed at the same time, so that residual stress remains in the underlying film, as shown in FIG.

This affects the pattern of the photosensitive resist (hereinafter referred to as resist), resulting in dimensional variations in the resist pattern, resulting in problems such as lack of stability and reliability.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide a highly reliable wafer pattern forming method by reducing the stress on the underlying film.

[Rounding method to solve the problem]

This invention exposes a wafer with a resist attached.

In a pattern forming method that involves development, a first step of exposing and developing only the dicing lines and etching;
After the first step, the resist is removed and a resist is applied again to form a circuit pattern.

Patterning of the wafer 1 is performed by a method including the N2 step, which is currently used.

[For production]

The wafer pattern forming method according to the present invention can reduce stress on the base film, and therefore can suppress finished dimensional variations.

〔Example〕

Hereinafter, one embodiment of the present invention will be explained with reference to the diagrams. 1st
Figures 4 to 4 are diagrams showing the steps of the wafer pattern forming method, in which Figure 1 is a perspective view of the wafer before processing, and Figure 2 shows the wafer in Figure 1 after photolithography and dicing. A perspective view of a wafer showing the optical state after line-only etching % Figure 3 is a sectional view taken along line A of Figure Wc2 with the resist removed from the state shown in Figure 2; FIG. 3 is a sectional view taken along line 8-m in FIG. 2 when a resist is applied from the state and one circuit pattern is patterned. In the figure, (1) is Ueno, % (2) is Regis)
, (N1 is the base film, and (4) is the dicing line.) Next, the operation will be explained. As shown in Figure 2, Ueno (1) turns only the dicing line (4) and removes the resist. As a result, by dividing the stressed base film (3) into smaller pieces along the dicing lines (4)K as shown in FIG. 3, the stress in the base film (3) can be dispersed.

Next, a second resist (2) is applied as shown in FIG.

Patterning the circuit pattern. If the stress on the base film (3) is large, the resist will easily peel off.

Easy to spread laterally. By first forming the dicing lines (4), lateral etching can be suppressed.

〔Effect of the invention〕

As described above, according to the present invention, the stress on the base film can be reduced by patterning only 2-in dicing prior to the patterning of the Ueno circuit pattern, so peeling of the resist can be suppressed, Effective in forming stable and reliable wafer patterns0

[Brief explanation of drawings]

FIGS. 1 to 4 are diagrams showing steps of a method for forming a pattern on a semiconductor wafer according to an embodiment of the present invention.
Figure 1 is a perspective view of the wafer before processing, Figure 2 is a perspective view of the wafer after etching only the dicing lines, and Figure 3 is a perspective view of the wafer after the resist has been removed from the state shown in Figure 2. 2 is a cross-sectional view at A and M in FIG. 2, and FIG. 4 is a cross-sectional view at A and M in FIG. 2 in a state where a circuit pattern has been patterned. . In the figure, (1) is the wafer, (2) is the resist% (3
) is the base film, and (4) is the dicing line. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A pattern forming method in which a photosensitive resist is applied to the entire surface of a semiconductor wafer on which a pattern is to be formed, and the semiconductor wafer with the photosensitive resist applied is exposed and developed, wherein only the dicing lines are exposed and developed. The first step is to perform etching.
After the step and the first step, the photosensitive resist is removed, a photosensitive resist is applied again, and the circuit pattern is exposed and developed. A method for forming a pattern on a semiconductor wafer, including a second step.