JPH0461384B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] The present invention provides a cache memory that equivalently realizes a large-capacity, high-speed memory by using a small-capacity, high-speed cache memory that holds a copy of a portion of the main memory.・Regarding memory control method. When a central processing unit (CPU) executes an instruction, it first provides an address in cache memory, and if the address is in cache memory, it refers to cache memory, otherwise it refers to main memory. Conventionally, when a read request to the main memory device is not approved by a priority judgment circuit that determines the priority of main memory requests, the same pipeline flow is started several times until permission is granted by the judgment circuit. By doing so, the request was sent to the main memory control unit (MCU). For this purpose, the request
There were times when there was a delay in sending data to the MCU, reducing system processing power. In the present invention, when this main memory read request is not approved by the determination circuit, the request is held in the main memory read port and the request is issued again from the port to the determination circuit, thereby delaying the above-mentioned delay. This makes it possible to realize efficient processing by minimizing. [Industrial Field of Application] The present invention provides a system for storing cache memory in a central processing unit (CPU) in response to instruction fetch and operand access requests coming from an I (Instruction) unit that executes control regarding instructions within the CPU. Control, particularly control of main memory read requests. In a computer system having a cache memory within the CPU, the time required to access the main memory is much longer than the time required to access the cache memory within the CPU. Therefore, in order to improve the processing performance of the system, when there is no data in the cache memory and a cache error occurs, the CPU sends a reference request to the main memory controller to retrieve valid data in the cache memory. It is necessary to transfer data more efficiently than the main memory. The present invention relates to a cache memory control method for executing main memory read requests at high speed. [Prior art] Central processing unit (CPU) and main storage unit (MSU)
A small-capacity, high-speed memory placed between the two is called cache memory. In general, the higher the speed of memory, the more expensive it is, so it is not economical to configure all large-capacity main memory (hereinafter referred to as main memory) with high-speed memory. The cache memory method, which realizes large-capacity, high-speed memory, is an extremely important technology for improving the processing speed of large computers. You can cache the parts of the instructions and operand data stored in main memory that will be used for the time being.
Store in memory. When the CPU executes an instruction,
The CPU first gives an address to cache memory. If the address is in cache memory, a cache hit occurs; if not, a cache miss occurs. While the cache is being hit, the CPU only refers to the cache memory, enabling high-speed processing. In the case of a cache miss, the CPU suspends instruction execution and writes data from main memory to cache memory. The constituent unit of each unit of cache memory is called a "block", and one block consists of several words. When exchanging the contents of cache memory and main memory, it is executed in blocks. In addition, in the case of a cache miss, when the CPU executes a write, the contents are written to the cache memory at that time, and the swap method writes the entire block to the main memory when the contents are exchanged, and the swap method writes the entire block to the main memory when the contents are exchanged. There is a store-through method that writes to both cache memory and main memory. FIG. 2 shows the system configuration of a computer when a cache memory is used. The CPU 10 is an I (Instruction) unit that decodes instructions and controls instructions.
an E (Execution) unit 101 that executes operations on operand data, and an I unit 100 that controls memory reading and writing to the cache memory and main memory.
S (Storage) unit 102 that controls cache hits and misses in response to requests from
It consists of CPU 10 is S unit 102
MCU11 (Main Storage Control
Unit (main memory control unit)), MCU11
In accordance with requests from the S unit 102, the main storage unit (MSU 12) controls reading and writing operations of the main storage unit (MSU 12). An operand request signal (OP) is sent from the I unit 100 to the S unit 102. REQ) and the fetch address (OP) for the operand request. REQ ADRS) is sent. Alternatively, the I unit 100 sends an instruction fetch request signal (IF REQ)
and the address (IF
REQ−ADRS) is sent. To answer this request, the S unit 102 examines its internal cache memory for operands or instructions, and if the cache memory contains the contents, that is, the cache hit, the OP STV
(OPERAND STATUS VALID) signal or IF
STV (INSTRUCTION FETCH STATUS
VALID) signal to the I-unit 100. At this time, the I unit can read and write from and to the cache memory. The I-unit 100 retrieves instructions from cache memory. CACHE DATA
receive as. Also, the E unit 101 OPENs the operand from the cache memory. CACHE
Receive as DATA. In case of cache miss, OP for each operand LMD
(OPERAND LINE MISSING DETECT) IF for signals and commands LMD (INSTRUCTION
FETCH LINE MISSING DETECT) signal. At this time, there is no requested content in the cache memory, so the S unit 102 sends the MS to the MCU 11. The REQ signal is issued to request main memory reference, and at the same time, the MS REQ ADRS
Give the reference address of. Also, the identification signal REQ for the request It also sends out an ID signal. And the MCU
11 accesses the main memory of MSU 12.
REQ The ID identifies operand block fetches, instruction block fetches, instruction prefetches, translation block fetches, etc. Data (MS) requested from MCU 11 to S unit 102 DATA) is sent, and at the same time the REQ Identification signal RTN equivalent to ID ID
is also sent. DATA The ID is an identification signal for controlling the order of data, etc. The address request (REQ) of an operand or instruction is P (Priority) in the S unit 102.
T (Translative address), B (Buffer access),
Processed in each of the four cycles of R (Result).
In the R cycle, if there is data in Buffer (cache memory), the data in cache memory is transferred to a general-purpose register in the CPU. LMD (OP LMD or IF
LMD) signal becomes active. At the same time, the S unit 102 REQ signal to MCU11
to request an exchange operation between the contents of main memory and the contents of cache memory. Said
When the LMD signal is issued, requests for operands or instructions following the request REQ are not processed in a pipeline manner, and processing is interrupted in the B cycle and T cycle, respectively. Next, a conventional cache memory control system and its operation will be explained using FIG.
OP The TEAR register 60 is a register that stores an operand request address in the T cycle. The OP The input to the TEAR register 60 is the operand request address (IU OP REQ ADRS), 61 operand ports (OP PORT) address from 0 to 2, 6
2nd OP This is selected from BFAR (Buffer Address) 0 to 3 in P cycle. OP
The requested address of the operand stored in TEAR60 is opened in T cycle. The logical address is converted into an absolute address using the TLB 63. At the same time, the operand cache directory (OP CACHE DIRECTORY) memory 64 and
The MATCH circuit 65 is used to check whether the address is in the cache. The signal indicating whether the cache hit is a mistake is OP in the B cycle. Set in DMR register 66. Also OP TLB63
Absolute address from OP BAAR register 67
is stored in In the case of a cache hit, the requested address is opened in the B cycle. BEAR(B
CYCLE EFFECTIVE ADDRES REGISTER)
Set in register 68 and OP CACHE
DATA Access ARRAY69 to read and write the cache. In the case of a cache miss, the absolute address is
MSAR (MAIN STORAGE ADDRES
REGISTOR) register 70, and its address is used to access the main memory via the MCU 11. Processing for the requested address of the instruction is executed in the lower circuit of FIG. 6, and is performed in the same manner as the control method for the operands described above. In the conventional method, the request address to the main memory read port is the MS Sending of the REQ signal is permitted. This requested address is set in the MSAR register 70, and at the same time the MSAR address is sent to the MCU 111. REQ signal is sent. At this time, MS to MCU11 Request addresses for which permission to send the REQ signal is not granted are not sent to the main memory read port, but are prepared separately 61
OP of It was stored in PORT0~2. 61 applicable
OP The output of PORT0~2 is not connected to the input of MSAR70, and OP is used to restart the pipeline. As PORTx signal, OP Return to TEAR register 60. That is, it was re-requested by sending it into the P cycle. This conventional cache memory control system will be further explained with reference mainly to the time chart of the conventional system shown in FIG. First, regarding the operation in each cycle shown in FIG. 5, the P cycle is a priority cycle, and the T/W
As explained in the circuit in Figure 6, a cycle is
OP This is an address conversion cycle by the TLB 63 and a directory search cycle by circuits 64 and 65, a B/S cycle is a data array read cycle or a data array write cycle by the circuit 69, and an R cycle is a result cycle. IU of REQ1 sent from I unit 100 OP REQ ADRS is OP for T cycle TEAR(OP T CYCLE
EFFECTIVE ADDRES REGISTER) 60 as an effective address and OP It is converted to an absolute address by TLB63, and it is opened as part of the effective address. CACHE DIRECTORY
64 is subtracted and a comparison is made with the absolute address. Then, in the B cycle, the absolute address is OP BAAR67 is set, and the comparison result in T cycle is OP Set in DMR66. If the comparison result in this T cycle does not match the WAY of any directory, that is, if there is a cache miss,
A fetch operation is performed on the MCU 11. First, the OP of B cycle OP from DMR66 The LMD signal is sent to the I unit 100 in the R cycle, and the OP The request address set in BAAR 67 undergoes a priority check to determine whether it is an operand block fetch request, an instruction block fetch request, or an operand store request. Then, only if permission is obtained, the requested address is used in the following R cycle.
MSAR70 and 62 OP It is stored in the vacant ports of BFAR0 to BFAR3. And from MSAR70
The requested address is sent to the MCU 11.
The MCU request source that becomes the input for MSAR70 is:
In this conventional method, OP BAAR67, IF
Each output of BAAR71 (operand and instruction block fetch request) and STAR of 72
(STORE ADDRES REGISTER) Up to three of the outputs 0 to 3 (operand store requests) conflict. In this conventional method, OP BAAR，IF
A control section that determines priorities in the order of BAAR and STAR0 to STAR3 is shown in FIG. On the other hand, OP
The address of BEAR68 remains open in the next R cycle. Stored in vacant ports PORT0-2. If permission is not obtained in the previous priority check, the requested address will be sent to 61 OP for the required period. PORT0~2
is maintained. Figure 5 Conventional RETRY
As shown in REQ1, such 61 OPs
OP the output of PORT0~2 PORTx signal, P
The request was restarted until it returned to the cycle and was given priority. If permission is not obtained in the above priority check, the MCU request (REQ1) is sent as shown in the timing chart of the conventional method in Figure 5.
is 61 OP The OP is stored in the vacant ports of PORT0 to PORT2, and in the second cycle one cycle after the end of R cycle of REQ1, the OP PORT0~
The request address of 2 is set as the effective address and sent to the same pipeline flow starting from P cycle,
RETRY REQ1 is activated. This is the second RETRY in this timing chart. With REQ1
It shows what MCU access permission was obtained, but actually this RETRY There is also a good chance that permission will not be obtained for REQ1. In this case, the above process will be repeated until permission is obtained. When sending the requested address to the MCU 11,
62 OP as shown in the control circuit in Figure 7.
The requested address is stored in BRAR0 to BRAR3, and as shown in the conventional method in Figure 5, each address is stored from R cycle.
VALID signal of BFAR0~3 (BFAR VALID)
is set. Along with that, BF In CNTL (block fetch control circuit) 75, MS
REQ signal and REQ that identifies the type of main memory read port, that is, the type of request ID is created and
The block fetch containing the operand is sent to the MCU 11. Note that the block fetch in this prior art is
It is done in 64Byte units, MS DATA is sent in eight byte units. When sending data from the MCU 11, the MS DATA (A, B, C, ..., H)
From the MCU 11 three cycles before the
EATA OUT WARNING (DOW) signal,
RTN ID (REQ ID and equivalent) signals and DATA Sending of the ID signal (signal indicating the type of data in the block) is started. These control signals cause the (OP MOVE IN REGISTER EVN) OP shown in the data system in Figure 9. MIR
EVN90, OP MIR ODD91 and MCU11
MS from DATA is set, and for each operand (OP CACHE DATA IN
REGISTER EVN）OP CDIR EVN92,
OP CDIR Transferred to ODD93. MOVE
IN is the OP shown in Figure 9. CDIR EVN92
and OP CDIR When data is set in both ODD93, OP CACHE DATA
The OP for ARRAY69 CDIR EVN92 and corresponding
OP CDIR This is a flow for writing the contents of the ODD 93 in the order of P, W, and S cycles. As shown in the time chart, it remains OP until MOVE IN ends, that is, until block fetch ends.
BFAR VALID continues to be sent. Bypass shown in the time chart of FIG. 5 is the request address from one unit 100 that started the block fetch request, and the data within the specified 8 bytes is OPENed. CACHE
DATA This shows a flow of writing to OWR (not shown), a general-purpose register in the CPU, without going through the ARRAY 69. The prior art related to block fetching of operands has been described above, but block fetching of instructions is also performed using similar control. [Problems to be Solved by the Invention] As described above, in the conventional system, a block fetch request to the host device is sent to the MCU access priority judgment circuit, that is, an operand block fetch request, an instruction block fetch request, or an operand block fetch request. If permission is not obtained in the judgment circuit for determining whether it is a store request, the request address is Stored in PORT0~2 and its output is OP again TEAR register 60
A reboot was performed to return to normal. According to this restart pipeline flow, it takes a long time to send the requested address to the main memory control unit (MCU), resulting in a problem that the processing efficiency itself decreases. [Means for Solving the Problems] A block diagram of the configuration of the cache memory control system of the present invention is shown in FIG. The operation of this embodiment is the same as that of the conventional example except for the operation when MCU access is not permitted. When MCU access is not permitted, that is, in the B cycle, when permission is not obtained in the priority check that determines which register contents are input to the MSAR register 70, in the present invention, the requested address is 62 OP It is stored in the vacant ports of BFAR0 to BFAR3. In other words, in the MCU access priority judgment circuit, even if permission is not granted, the requested address is sent to OP62. BFAR0～3
It is possible to store the output once in , and retransmit the output as input to the priority determination circuits 20 and 21.
This allows the request to be subsequently used as a request source for priority determination. if
OP If there is no free port in BFAR0~3, 61 OP The data is stored in PORT0 to PORT2, and the same processing as in the conventional example is performed. 62 OP BFAR0
Since request addresses for which MCU access has been granted are also stored in .about.3, this distinction is made by the flag. In this way, the present invention uses the conventional OP as an MCU request source. BAAR，IF BAAR,
In addition to the three STARs 0 to 3, there is a new OP
In addition to the outputs of BFAR0 to BFAR3, there are a maximum of four. [Function] The main memory read port of the present invention allows the MCU access priority determination circuit to send the requested address to 62 even if permission is not granted.
OP The signal is stored in BFAR0 to BFAR3, and its output is input to the priority determination circuit so that it can be retransmitted. [Embodiment] First, the cache memory control method of the present invention will be explained using the system configuration diagram of a computer shown in FIG. IU from I unit 100 REQ VALID
For example, when the S unit 102 receives an operand request by a signal, it requests the I unit 100 if the operand exists in the cache memory.
OP Returns STV (OP STATUS VALID) signal. If the operand is not in cache memory, the I-unit 100 (OP
LINE MISSING DETECT）OP In addition to returning the LMD signal, the MS A block fetch including the operand is performed by sending the REQ signal and causing the MCU 11 to control the main storage unit (MSU) 12. An explanatory diagram of the address control system of the present invention relating to the block fetch and its time chart are shown in FIGS. 1 and 5, respectively, and the cache memory control system of the present invention will be explained with reference to these figures. In FIGS. 1 and 5, for example, the operand request is P (Priority), T
(Translative address), B (Buffer access), R
(Result) is processed in each of the four cycles. R
During a cycle, if there is no data in the Buffer (cache memory), a block fetch is performed, and if there is, the data in the cache memory is transferred to a general-purpose register in the CPU. 1st
Diagram OP The output signal of DMR register 66 is OP
DIRECTO RY MATCH This is a REGISTER signal that becomes active when there is requested data in the cache, and becomes inactive when there is not. OP When the DMR66 is inactive and there is no data in the cache, the LMD signal (OP LMD) becomes active. At the same time, the S unit 102
M.S. The REQ signal is sent to the MCU 11 to read data from the main memory. When the LMD signal is issued, operand requests subsequent to the operand request are interrupted. OP TEAR60 is a register that stores the operand request address in T cycle. Applicable
OP Input to TEAR60 is I unit 100
Operand request address (IU) from OP REQ
ADRS), 61 operand ports (OP
Addresses from PORT0~2), 62 buffer addresses (OP BFAR0 to BFAR3) are selected in P cycle. OP The requested address of the operand stored in TEAR60 is opened in T cycle.
The logical address is converted into an absolute address using the TLB 63. At the same time, the operand cache directory (OP CACHE
DIREC TORY) Memory 64 and MATCH circuit 6
5 to check whether the address is in the cache. The cache hit or miss signal is OP in B cycle. Set in DMR66. Also, OP Absolute address from TLB63 is OP Stored in BAAR67. cashier
In the case of a hit, the requested address is opened in the B cycle. Stored in BEAR68, OP CACHE
DATA Access ARRAY69 to read and write from the cache. In the case of a cache miss, if the control signal 201 from the control signal source 20 of the priority determination circuit is selected by the selector 21 of the priority determination circuit in the R cycle, the absolute address but
MSAR (MAIN STORAGE ADDRESS
REGISTER) 70. and,
That address within MSAR 70 is used to access main memory via MCU 11. Control of requests for instructions, as well as operands, is performed in the lower circuit of FIG. The cache memory control method according to the present invention will be explained in detail with reference to FIG. 5, a time chart of the method according to the present invention. First, for each cycle shown in FIG. 5, the P cycle is the priority cycle, and the T/W cycle is the OP cycle. TLB6
The B/S cycle is an address conversion by circuit 69 and a directory search cycle by circuits 64 and 65. The B/S cycle is a data array read cycle/data array write cycle by circuit 69.
A cycle is a result cycle. I
IU of REQ1 sent from unit 100 OP
REQ ADRS is OP for T cycle TEAR
60 as a valid address and OP
The TLB 63 converts it into an absolute address. Along with that, OP with part of the valid address
CACHE DIRECTORY64 is subtracted and compared with the absolute address. Then, in the B cycle, the absolute address is OP BAAR67 is set, and the comparison result in T cycle is OP
BAAR67 is set. The comparison result in this T cycle is the WAY of which directory.
If they do not match, that is, if a cache miss occurs, a fetch operation is performed on the MCU 11. First, the OP of B cycle DMR66
More OP LMD signal is R cycle and I unit 1
00 and the OP The requested address set in the BAAR 67 is input to the selector 21 of the priority determination circuit. These judgment circuits 20 and 21 determine whether the request is an operand block fetch request, an instruction block fetch request, an operand store request, or 62, along with other MCU requests.
OP It is determined whether to give priority to the outputs of BFAR0 to BFAR3. OP The request address set in BAAR 67 receives the priority check, and only if permission is obtained is the R cycle that follows.
Stored in MSAR70. And MSAR70
The request address is sent to the MCU 11.
The MCU request source that becomes the input for MSAR70 is:
In the method of the present invention, OP BAAR67, IF
Each output of BAAR 71 (operand and instruction block fetch request) and 72
STAR0~3 output and 62 new OPs
Up to four of the outputs of BFAR0-3 will compete. OP BFAR0~3, OP BAAR，IF
The control section of the priority determination circuits 20 and 21 that determine priorities in the order of BAAR and STAR0 to STAR3, that is, the MSAR input selector control section of the present invention is shown in FIG. In this circuit BFARx
When the VALID signal is valid, the address in BFARx62 is selected and BFARx OP when VALID signal is invalid BAAR OP when VALID signal is valid
The address in BAAR67 is selected, the former two VALID signals are invalid, and the IF BAAR VALID
When the signal is valid, IF The address in BAAR71 is selected, the former three VALID signals are invalid,
STAR An address within STAR 72 is selected when the VALID signal is valid. The selected address is
It is set in MSAR 70 and sent to MCU 11. When MCU access is not permitted, that is, when MCU access is not permitted by the priority check in cycle B, in this embodiment, the block fetch request address is 6.
2nd OP It is stored in the vacant ports of BFAR0 to BFAR3. OP if there are no free ports PORT0～
2, and the same processing as in the conventional example is performed. The process to be performed when permission is not obtained in the above priority check will be explained using the timing chart of the system of the present invention in FIG. REQ
MCU requests for which permission was not obtained in 1.
As explained earlier, 62 OP It is stored in the vacant ports of BFAR0 to BFAR3. In the present invention, in the first cycle after the R cycle of REQ1 is completed, such 62
OP Request addresses from BFAR0~3 are sent to circuit 22
is activated as an input to the selector 21 in FIG. Figure 5 Timing chart of the present invention method shows the second MS Although it is shown that permission for the MCU address has been obtained in the REQ, in reality this MS There is also a good chance that permission will not be obtained in the REQ. In this case, the above process (priority check on MSAR) will be repeated. When sending the block fetch request address to the MCU 11, the request address is stored in 62 BFARs 0 to 3, as shown in the BFAR output selector control section of FIG. ~3VALID signal is set. 62 OP For BFAR0~3,
Since MCU access permissions are also stored, in addition to port valid flags (BFAR0 to 3VALID) for this distinction, MCU requests (MS REQ) Request flags (BFAR0 to 3REQ) are prepared to indicate whether or not to send the data. The MCU access permission request has only the valid flag set among the above flags, and its contents are held until the block fetch operation is completed.
In the case of an MCU access disallowance request, both flags are set at the same time as the data is stored in the port.
The request flags (BFAR0 to 3REQ) are reset when MCU access permission is obtained, and their contents are held until the block fetch operation is completed. In other words, the circuit in Figure 3 has BFAR0
When REQ is enabled, BFAR0 is selected and
BFAR0 REQ is invalid and BFAR1 BFAR1 is selected when REQ is valid, BFAR2 is selected when the above two REQs are invalid. When REQ is valid, BFAR2 is selected, and when the three REQs are invalid, BFAR3 is selected and enters the MSAR 70 via the decoder 21. [Effects of the Invention] According to the present invention, as long as there is space in the main memory read port, requests that are not allowed for MCU requests can also be stored, thereby restarting the pipeline flow that was conventionally performed. This eliminates the need for high-speed and efficient processing.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of an address control system related to block fetch using the cache memory control method of the present invention, FIG. 2 is a configuration diagram of a computer system having a cache memory, and FIGS. 3 and 4 are each according to the present invention. A configuration diagram of the BFAR output selector control unit and MSAR input selector control unit according to the method,
FIG. 5 is a time chart for the conventional method and the method of the present invention, FIG. 6 is a block diagram of the address control system related to block fetch by the conventional cache memory control method, and FIGS. 7 and 8 are BFAR of the conventional method. FIG. 9, which shows the control units of the output selector and the MSAR input selector, is a configuration diagram of the DATA system common to the present invention method and the conventional method. 100...Central processing unit (CPU), 11...Main memory control unit (MCU), 12...Main storage unit (MSU), 20...Control signal source, 21...Selector, 22...Priority determination circuit , 60...
OP that stores operand request address in T cycle TEAR register, 61...OP
PORT0~2,62...BFAR0~3,63...
OP to convert logical address to absolute address
TLB, 64...operand cache directory memory, 65...MATCH circuit, 6
6...OP that sets a signal indicating that the bit in the cache is a mistake. DMR register, 67... BAAR register that stores the absolute address, 68... OP that stores the requested address of the cache hit
BEAR register, 69... Operand cache data array, 70... MSAR register that stores the absolute address in case of cache miss.
71...IF BAAR register, 100...instruction
(I) Unit, 101... Execution (E) Unit, 102
...S (Storage) unit.

Claims (1)

[Claims] 1. Instruction control unit 10 in central processing unit 10
0 gives an address to the cache memory that holds part of the contents of the main memory 12, and if the address exists in the cache memory, controls the cache hit, and if the address does not exist, controls the main memory controller 11. In the cache memory control unit 102 that accesses and makes a main memory reference request to the main memory device 12, a priority control unit selects various requests to the main memory control device regarding reading or writing of instructions or operands in accordance with priority. Judgment circuits 20 and 21, and when the priority judgment circuits 20 and 21 do not approve a request to the main storage control device 11, the request is held and the request is sent to the priority judgment circuits 20 and 21 again. A cache memory control system characterized by having a plurality of main memory read ports including at least one port 62 for issuing requests. 2. Inputs to the selector 21 of the priority determination circuit that selects requests to the main memory control device 11 are operand and instruction block fetch requests 67 and 71, and operand store requests 7.
2, and the priority determination circuit 20, 2
and a request from a port 62 that holds the request and re-issues the request to the priority determination circuits 20 and 21 if permission is not granted in the cache according to claim 1.・Memory control method.