JPH0461935U - - Google Patents

Description

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an A/D converter according to an embodiment of this invention, and FIG. 2 is a diagram showing analog signal waveforms input to the A/D converter from the outside.
Figure 3 is a diagram showing the reference signal waveform output by the reference waveform generator, Figure 4 is a diagram showing the digital signal waveform output from the encoder, Figure 5 is a diagram showing the digital signal waveform output from the adder, and Figure 6 is a diagram showing the digital signal waveform output from the adder. The figure shows a digital signal waveform output from an encoder of a conventional A/D converter, FIG. 7 shows a digital signal waveform output from a coefficient data generator, and FIG. 8 shows an implementation of a conventional A/D converter. FIG. 2 is a block diagram showing an example. In the figure, 1 is a reference waveform generator, 2 is a voltage dividing resistor, 3 is a comparator, 4 is an encoder, 5 is an adder, 6 is a reference voltage source, 7 is a coefficient data generator,
8 multiplier. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (1)

[Scope of utility model registration request] A reference waveform generator that outputs a reference waveform represented by an impulse response of a low-pass filter, a voltage dividing resistor that attenuates the reference waveform output from the reference waveform generator to a desired amplitude, and an externally input analog signal. A comparator that compares the voltage of the reference waveform attenuated by the voltage dividing resistor, an encoder that converts the comparison result of the comparator into a binary code, and an adder that sequentially adds the time series digital signals output from the encoder. A/D converter.