JPH04622Y2 - - Google Patents
Info
- Publication number
- JPH04622Y2 JPH04622Y2 JP15005180U JP15005180U JPH04622Y2 JP H04622 Y2 JPH04622 Y2 JP H04622Y2 JP 15005180 U JP15005180 U JP 15005180U JP 15005180 U JP15005180 U JP 15005180U JP H04622 Y2 JPH04622 Y2 JP H04622Y2
- Authority
- JP
- Japan
- Prior art keywords
- level
- circuit
- synchronization signal
- signal
- video signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims description 12
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 239000002131 composite material Substances 0.000 claims description 4
- 230000003321 amplification Effects 0.000 description 4
- 238000003199 nucleic acid amplification method Methods 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 238000007493 shaping process Methods 0.000 description 2
- 101000659071 Homo sapiens Synergin gamma Proteins 0.000 description 1
- 102100035600 Synergin gamma Human genes 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Landscapes
- Television Receiver Circuits (AREA)
- Television Signal Processing For Recording (AREA)
Description
【考案の詳細な説明】 本考案は同期信号レベル制御回路に関する。[Detailed explanation of the idea] The present invention relates to a synchronization signal level control circuit.
従来、VTR(ビデオテープレコーダ)では、映
像信号処理回路において、AGC回路を設け、記
録される映像信号のレベルが常に一定になるよう
にしている。そして、AGC回路には一般に
SYNC,AGCが採用されており、このSYNC,
AGCとは映像信号中の映像の明暗に無関係な水
平同期信号のレベルのみに着目し、この同期信号
レベルを常に一定になるように制御することによ
り映像信号のレベルを常に一定にしようとするも
のである。例えば、1VPPの映像信号で同期信号
が0.3VPPの信号を基準にとれば、同期信号部分
が映像信号全体の30%の信号であると、入力信号
のレベルの大小に拘わらず、出力は常に1VPPと
なる。 Conventionally, in a VTR (video tape recorder), an AGC circuit is provided in the video signal processing circuit to ensure that the level of the recorded video signal is always constant. And the AGC circuit generally has
SYNC, AGC is adopted, and this SYNC,
AGC is a system that focuses only on the horizontal synchronization signal level, which is unrelated to the brightness of the video signal, and attempts to keep the video signal level constant by controlling this synchronization signal level so that it is always constant. It is. For example, if you take a 1VPP video signal and a synchronization signal of 0.3VPP as a reference, if the synchronization signal portion is 30% of the entire video signal, the output will always be 1VPP regardless of the input signal level. becomes.
一般に映像信号レベルに対する同期信号レベル
の割合(同期信号比率)が上述のように30%とさ
れているが、通常のテレビジヨン放送において
は、同期信号レベルが放送局によつて多少変動
し、また、受像機の映像検波回路や高周波増巾、
中間周波増巾回路では、映像信号のうちの同期信
号が回路の非直線歪を受け易く、一般に検波出力
は入力信号に比べて同期信号部分が縮んで出力さ
れることが多い。そのため、前述と同様に、
1VPPの映像信号で同期信号が0.3VPPの信号を
基準にとれば、今、映像信号が1VPPであつても
同期信号が縮んで0.15VPPしかなければ、AGC
回路が、0.15VPPの同期信号を0.3VPPにするよ
うに映像信号を増巾し結果として映像信号が
2VPPになつてしまうため、FM変調時に過変調
を生じるおそれがある。 Generally, the ratio of the synchronization signal level to the video signal level (synchronization signal ratio) is set at 30% as mentioned above, but in normal television broadcasting, the synchronization signal level varies somewhat depending on the broadcasting station, and , video detection circuit and high frequency amplification of the receiver,
In an intermediate frequency amplification circuit, the synchronization signal of the video signal is susceptible to nonlinear distortion of the circuit, and generally the detection output is often output with the synchronization signal portion shrunk compared to the input signal. Therefore, as mentioned above,
If we take a signal with a 1VPP video signal and a synchronization signal of 0.3VPP as a reference, even if the video signal is 1VPP, if the synchronization signal is shrunk to only 0.15VPP, then AGC
The circuit amplifies the video signal so that the 0.15VPP synchronization signal becomes 0.3VPP, and as a result, the video signal becomes
Since it becomes 2VPP, overmodulation may occur during FM modulation.
このため、映像信号出力が1VPPをオーバーす
る場合にはホワイトピークを検出するピーク
AGCを動作せしめてビデオ信号を1VPP以内に納
めるようにしているが、このピークAGCが動作
すると、前述の同期信号比率が変わるという欠点
がある。 Therefore, if the video signal output exceeds 1VPP, the peak at which the white peak is detected is
AGC is activated to keep the video signal within 1VPP, but when this peak AGC is activated, the above-mentioned synchronization signal ratio changes.
本考案は上述の欠点を解消すべくなされたもの
でありAGC回路の出力レベルを検出し、このレ
ベルが所定値以上の場合、このレベルに応じて
AGC回路に入力される映像信号の同期信号比率
を一定値に近づけるようにした同期信号レベル制
御回路を提供するものである。 This invention was made to eliminate the above-mentioned drawbacks, and detects the output level of the AGC circuit, and if this level is higher than a predetermined value, the
The present invention provides a synchronization signal level control circuit that brings the synchronization signal ratio of a video signal input to an AGC circuit close to a constant value.
以下、図面に従つて本考案の一実施例を説明す
る。 An embodiment of the present invention will be described below with reference to the drawings.
図面は本考案回路の概略ブロツク図を示してお
り、1は複合映像信号が入力される入力端子、2
は該入力端子1からの複合映像信号の水平同期信
号のレベルが低下した場合、伸長して同期信号比
率を正規の値、すなわち30%に近づくよう制御す
る同期レベル可変伸長回路、3はAGC制御増巾
器31、同期分離回路32及び同期レベル検出回
路33の閉ループで形成されるSYNG,AGC回
路で、同期信号レベルを常に一定に保つように動
作する。4は前記同期分離回路32出力を増巾整
形して前記同期レベル可変伸長回路2に入力する
増巾整形回路、5は前記SYNC,AGC回路3出
力が所定値以上、例えば1VPP以上の時のピーク
レベルを検出するピークレベル検出回路、6は該
ピークレベル検出出力を整流して前記同期レベル
可変伸長回路2に入力する整流回路で、前記同期
レベル可変伸長回路2及びピークレベル検出回路
5と共に閉ループを形成する。7は出力端子であ
る。 The drawing shows a schematic block diagram of the circuit of the present invention, in which 1 is an input terminal into which a composite video signal is input, 2 is an input terminal to which a composite video signal is input;
3 is a synchronization level variable expansion circuit that expands and controls the sync signal ratio to approach the normal value, that is, 30%, when the level of the horizontal synchronization signal of the composite video signal from input terminal 1 decreases; 3 is an AGC control The SYNG and AGC circuits are formed by a closed loop of an amplifier 31, a sync separation circuit 32, and a sync level detection circuit 33, and operate to keep the sync signal level constant. 4 is an amplification shaping circuit that amplifies and shapes the output of the sync separation circuit 32 and inputs it to the sync level variable expansion circuit 2; 5 is a peak when the output of the SYNC and AGC circuit 3 is above a predetermined value, for example 1 VPP or above; A peak level detection circuit 6 is a rectifier circuit that rectifies the peak level detection output and inputs it to the synchronous level variable expansion circuit 2, which forms a closed loop together with the synchronous level variable expansion circuit 2 and the peak level detection circuit 5. Form. 7 is an output terminal.
次に上述の構成の回路動作について説明する。 Next, the operation of the circuit having the above configuration will be explained.
今、正規の映像信号のレベルを1VPP、同期信
号比率を30%とすると、入力端子1より入力され
る映像信号の同期信号比率が30%である場合、
SYNC,AGC回路3出力は1VPPの正規な映像信
号となつて出力端子7に導出される。 Now, assuming that the regular video signal level is 1VPP and the synchronization signal ratio is 30%, if the synchronization signal ratio of the video signal input from input terminal 1 is 30%, then
The output of the SYNC and AGC circuit 3 becomes a 1VPP regular video signal and is led out to the output terminal 7.
次に入力される映像信号の同期信号のみが縮ん
でいる場合、すなわち同期信号比率が小さい場
合、SYNC,AGC回路3では同期信号が正規の
レベルになるように映像信号全体を増巾するの
で、SYNC,AGC回路3出力は1VPP以上とな
る。そこで、SYNC,AGC回路3出力が1VPPを
越える場合、ピークレベル検出回路5が動作して
ピークレベルを検出し、この検出出力は整流回路
6で整流されて増巾整形回路4出力と共に同期レ
ベル可変伸長回路2に入力され、同期信号期間、
同期信号レベルのみを伸長して正規の同期信号比
率に近づくように制御する。 If only the synchronization signal of the next input video signal is compressed, that is, if the synchronization signal ratio is small, the SYNC/AGC circuit 3 amplifies the entire video signal so that the synchronization signal becomes the normal level. SYNC, AGC circuit 3 output will be 1VPP or more. Therefore, when the SYNC and AGC circuit 3 output exceeds 1VPP, the peak level detection circuit 5 operates to detect the peak level, and this detection output is rectified by the rectifier circuit 6, and the synchronization level can be adjusted together with the amplification shaping circuit 4 output. input to the expansion circuit 2, the synchronization signal period,
Control is performed so that only the synchronization signal level is expanded to approach the normal synchronization signal ratio.
従つて、この同期レベル可変伸長回路2で同期
信号レベルを伸長された映像信号はSYNC,
AGC回路3で1VPPとされて出力端子7に導出さ
れる。 Therefore, the video signal whose synchronization signal level has been expanded by this synchronization level variable expansion circuit 2 is SYNC,
The AGC circuit 3 converts it to 1VPP and outputs it to the output terminal 7.
上述の如く本考案によれば、テレビジヨン受像
機の映像検波回路等で同期信号のみが縮んだ映像
信号をSUNC,AGC回路の前段において同期信
号のみを伸長して同期信号比率を正規の値に近づ
けてやることによつて、SYNC,AGC回路出力
が正規の値を越えることがなく、FM変調時の過
変調を防止することができる。 As described above, according to the present invention, a video signal in which only the synchronization signal has been compressed in the video detection circuit of a television receiver is SUNC, and only the synchronization signal is expanded in the previous stage of the AGC circuit to bring the synchronization signal ratio to a normal value. By bringing them close together, the SYNC and AGC circuit outputs will not exceed the normal values, and overmodulation during FM modulation can be prevented.
図面は本考案の一実施例における同期信号レベ
ル制御回路の概略ブロツク図である。
主な図番の説明、2……同期レベル可変伸長回
路、3……SYNC,AGC回路、5……ピークレ
ベル検出回路。
The drawing is a schematic block diagram of a synchronizing signal level control circuit according to an embodiment of the present invention. Explanation of main drawing numbers, 2... Synchronous level variable expansion circuit, 3 ... SYNC, AGC circuit, 5... Peak level detection circuit.
Claims (1)
ルを制御するAGC回路の前段に設けられる複合
同期信号の水平同期信号レベルを可変伸張する同
期レベル可変伸張回路と、前期AGC回路の後段
に設けられAGC回路出力が所定レベルを越えた
時のピークレベルを検出するピークレベル検出回
路とを備えていて、前期同期レベル可変伸張回路
では、該ピークレベル検出回路の出力と同期信号
を入力して、同期信号期間に同期信号レベルのみ
を伸張して映像信号の同期信号比率を正規の値に
近づけることを特徴とする同期信号レベル制御回
路。 A variable synchronization level expansion circuit that variably expands the horizontal synchronization signal level of the composite synchronization signal is installed before the AGC circuit that detects the horizontal synchronization signal level and controls the level of the video signal, and an AGC circuit is installed after the previous AGC circuit. It is equipped with a peak level detection circuit that detects a peak level when the circuit output exceeds a predetermined level, and the first stage synchronous level variable expansion circuit inputs the output of the peak level detection circuit and a synchronous signal, and detects the synchronous signal. A synchronization signal level control circuit that extends only the synchronization signal level during a period to bring a synchronization signal ratio of a video signal close to a normal value.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15005180U JPH04622Y2 (en) | 1980-10-20 | 1980-10-20 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15005180U JPH04622Y2 (en) | 1980-10-20 | 1980-10-20 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5772669U JPS5772669U (en) | 1982-05-04 |
| JPH04622Y2 true JPH04622Y2 (en) | 1992-01-09 |
Family
ID=29509428
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15005180U Expired JPH04622Y2 (en) | 1980-10-20 | 1980-10-20 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04622Y2 (en) |
-
1980
- 1980-10-20 JP JP15005180U patent/JPH04622Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5772669U (en) | 1982-05-04 |
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