JPH046316B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a color signal recording device and method for a video tape recorder, which is suitable for IC implementation.

High-density video tape recorder (hereinafter referred to as VTR)
This makes tracking during recording and playback difficult. A conventional technique for solving this problem is a system in which a pilot signal is superimposed on a video signal and recorded, and the pilot signal is detected during playback to control the tape running direction. The circuit for generating this pilot signal is composed of an X-tal oscillator and a high-speed frequency dividing circuit in order to maintain tape compatibility, so there is a problem that it is difficult to integrate into an IC and is economically inefficient. The problems of this prior art will be explained in detail with reference to FIG.

FIG. 1 is a block diagram illustrating the prior art. In the figure, 1 is an input terminal for a recording color signal having a frequency f _SC , 2 is an input terminal for a reproduced color signal having a frequency f _LSC , 11 is a switch circuit that is switched to the position shown during recording, and 12 is a frequency f _CONU . f _CONU −f _SC when recording as a carrier signal as an output signal
and f _CONU + f _SC , a first frequency conversion circuit (hereinafter referred to as converter) that obtains the signals of f _CONU - f _LSC and f _CONU + f _LSC during playback, and 13 converts the low frequency f _CONU - f _SC during recording. Low-pass filter for extracting gamut color signals, 16
Reference numeral 5 indicates an adder circuit for adding a low-range color signal and a pilot signal to be described later, and 5 an output terminal for a color signal during recording. Reference numeral 14 designates a bandpass filter for extracting the color signal of the frequency f _CONU -f _LSC during reproduction, 15 represents a reproduction color signal processing circuit, and 6 represents a color signal output terminal during reproduction.
24 is a phase locked circuit that generates a carrier signal S _VCO of Nf _H (N is an integer, f _H is a horizontal scanning frequency);
17 is a voltage controlled oscillator ( _hereinafter referred to as
18 is a 1/N frequency divider circuit, 19 is a phase detector, and 4 is a horizontal pulse input terminal. 41 is a 1/8 frequency divider circuit, 20 is a phase shift circuit, 21 is a phase synchronization circuit composed of an Xtal oscillator with an oscillation frequency f _SC , and 22 has a carrier with an input frequency f _SC and a signal of f _LSC , f _SC + f The second converter 23, which outputs a signal of _LSC and f _SO -f _LSC , outputs a signal of f _SC + f _LSC = f _CONU . Here, the phase shift circuit 20 is NTSC
In the case of the recording color signal frequency f _LSC , the conditions of ``having an offset of 1/4 f <sub>H</sub> '' and ``having a frequency difference of an odd multiple of 1/2 f _H between fields'' must be satisfied at the same time. Configure. In addition, in the case of the PAL system, the recording color signal frequency f _LSC conditions "to have an offset of 1/8 f _H " and "to have a frequency difference between fields that is an odd multiple of 1/4 f _H " are simultaneously satisfied. Configure.

On the other hand, 40 is a pilot signal generation circuit.
25 is the Xtal oscillator with oscillation frequency f _OSC , 26,2
Numerals 7, 28, and 29 are frequency dividing circuits that divide the oscillation frequency f _OSC of the Xtal oscillator into frequencies f ₁ , f ₂ , f ₃ , and f _{4 ,} respectively, and 30 is a frequency selection circuit. The frequency selection circuit 30 selects f ₁ for the first field, f ₂ for the second field, f ₄ for the third field, and f 3 for the fourth field according to the signal at the head pulse input terminal ₃ . be recorded in the prescribed order. The frequency of the pilot signal is generally selected to be lower than the frequency band of the low-range color signal, such as f ₁ 6.5f _H , f ₂ 7.5f _H , f ₃ 9.5f _H , and f ₄ 10.5f _H . Also, the oscillation frequency of the X-tal oscillator
f _OSC is set to a sufficiently high frequency to reduce the frequency variation of the pilot signal, for example, the frequency division ratios of f _OSC 4.91MHz314f _H frequency divider circuits 26 to 29 are 1/l ₁ , 1/l ₂ , 1/ If l ₃ and 1/l ₄ , then l ₁ = 48 f ₁ 6.5f _H l ₂ = 42 f ₂ 7.5f _H l ₃ = 33 f ₃ 9.5f _H f ₄ = 30 f ₄ 10.5f _H.

The reproduced pilot signal is inputted from the reproduced color signal input terminal 2 and processed by a tracking signal generation circuit 39. In the tracking signal generating circuit 39, the pilot signal is separated by a low pass filter 31. 32 is a reset circuit for making the pilot frequency selection order during playback match that during recording;
A third converter 33 outputs a signal obtained by multiplying the reproduced pilot signal by the output signal of the frequency selection circuit. 34 is a first frequency discrimination circuit with a center frequency f _H , 35 is a second frequency discrimination circuit with a center frequency 3f _H , 36 is a differential amplifier, 37 is an inverting amplifier, and 38 is an output signal of the differential amplifier CH- 1
If you want to play the track of
7 is a tracking signal output terminal. The output signal from the tracking output terminal 7 is supplied to a tape running direction control circuit (not shown) to control the tape playback speed.

FIG. 2 is a diagram showing the tracks recorded on the tape and the position of the playback head. 2a to 2f are the tracks, 2l to 2o are the positions of the reproducing head when tracking is normal, 2g to 2k are the positions of the reproducing head when tracking is deviated, and 2p is the tape running direction. The frequencies of the pilot signals recorded on the tape are f ₁ , f ₄ , f 1 , and CH for tracks 2b, 2d, and _2f recorded by the recording head of CH-1, respectively.
Tracks 2a, 2 recorded with recording head -2
c and 2e are f ₃ , f ₂ and f ₃ respectively. In addition, when reproducing a track recorded on CH-1 (for example, 2b, 2d, 2f), the changeover switch 38 is set to the position shown in the figure, or to CH-2 (for example, 2a, 2c, 2e).
In this case, switch to the opposite position as shown.

Track 2b when the playback head is in position 2l to 2o.
When tracking is normal for ~2e, the frequency of the reproduced pilot signal is
f ₁ , f ₂ , f ₃ , f ₄ . On the other hand, frequency selection circuit 3
Since the output of 0 is selected by the reset circuit 32 to correspond to the same frequency as that at the time of recording, the following frequency is output as the output of the third converter 33.

For track 2b, f ₁ - f ₁ = 0 and f ₁ + f ₁ = 6.5f _H + 6.5f _H = 13f For track 2c, f ₂ - f ₂ = 0 and f ₂ + _{f 2 =} 7.5 f _H +7.5f _H = 15f f ₄ - f ₄ = 0 for _H track 2d and f ₄ + f ₄ = 10.5f _H + 10.5f _H = 21f f ₃ - f ₃ = for _H track 2e. 0 and f ₃ +f ₃ =9.5f _H +9.5f _H =19f _H Therefore, the first frequency discrimination circuit 34, the second
No output is generated in any of the frequency discrimination circuits 35, and the output of the differential amplifier 36 is "0".

Next, a case will be explained in which the running speed of the tape is slow and the position of the reproducing head is shifted like 2g, 2h, 2i. When the playback head is at position 2g with respect to track 2b of CH-1, the playback pilot frequency is two frequencies, _f3 and _f1 , and the output of the third converter 32 is _f1 - _f1 = 0 _f1 + f. Four frequencies are output: ₁ = 6.5f _H + 6.5f _H = 13f _H f ₃ −f ₁ = 9.5f _H −6.5f _H = 3f _H f ₃ +f ₁ = 9.5f _H + 6.5f _H = 16f _H. Ru. In this case, the second frequency discrimination circuit ₃₅ with a center frequency of 3f _H
-f ₁ =3f _H is detected, a negative voltage is generated at the differential amplifier 36 and the tracking signal output terminal 7, the running speed of the tape is controlled to be increased, and the tape is returned to the position 2l of the reproducing head. When the reproducing head is at position 2h with respect to track 2c of CH-2, pilot signals of f ₁ and f ₂ are reproduced, and the output of the third converter 32 is f ₂ −f ₁ =7.5f _H −6.5f _H Four frequencies including the frequency = _fH are output.
In this case, an output is generated in the first frequency discrimination circuit 34 having the center frequency _fH , and a positive voltage is generated in the differential amplifier 36. In this case, as described above, since the changeover switch 38 is switched in the opposite direction to that shown, a negative voltage is generated at the tracking output terminal 7, and the same control as described above is performed. CH-1 track 2d
On the other hand, when the playback head is at position 2i, pilot signals of f ₂ and f ₄ are played back, and track 2 of CH-2 is played back.
When the reproducing head is at position 2j with respect to e, pilot signals of f ₄ and f ₁ are generated. Therefore, the outputs of the third converter 32 each include a frequency f ₄ −f ₂ =10.5f _H −7.5f _H =3f _H f ₄ −f ₃ =10.5f _H −9.5f _H =f _H Four frequencies are output, and positive voltages are generated at the tracking signal output terminal 7, so that the same control as described above is possible.

On the other hand, a case will be explained in which the running speed of the tape is high and the positions of the reproducing heads are 2h, 2i, 2j, and 2k. In the above case where the reproduction head is 2h for track 2b of CH-1, the pilot signals of f ₁ and f ₂ are reproduced, and the output of the third converter 32 is f ₂ −f ₁ =7.5f _H −6.5f. Four frequencies including the frequency _H = f _H are output.
In this case, the first frequency discrimination circuit 35 output is generated and a positive voltage of the differential amplifier 36 is generated.
Therefore, a positive voltage is generated at the tracking signal output terminal 7 and, contrary to the above, a negative voltage is generated, the tape running speed is controlled to be slow, and the position of the reproducing head is returned to 2L. Track 2b, 2c, 2
At positions 2i, 2j, and 2k of the reproduction head with respect to d, pilot signals of f ₂ and f ₄ , f ₄ and f ₃ , and f ₃ and f ₁ are reproduced, respectively. Therefore, the output of the third converter 32 has respectively f ₄ −f ₂ =10.5f _H −7.5f _H =3f _H f ₄ −f ₃ =10.5f _H −9.5f _H =f _H f ₃ −f ₁ = 9.5f _H -6.5f _H = 3f Since four frequencies including the frequency _H are output, a positive voltage is generated at the tracking signal output terminal 7 in all cases, slowing down the running speed of the tape. control to return the playback head position to its normal position.

The problem here is that the X-tal oscillator 25 requires an expensive Xtal element, and this
Since the oscillation frequency f _OSC of the oscillator 25 is as high as MHz,
For example, an ECL (Emitter Coupled
(Loqic) requires similar high-speed logic elements. Therefore, when implementing CI, the number of external H components, chip area, and power consumption will increase.

The purpose of the invention is to eliminate the drawbacks of the prior art and
The object of the present invention is to provide a color signal recording device that can be easily integrated into an IC.

In the present invention, Nf _H is used for low-frequency conversion of color signals.
(N: integer, _fH horizontal synchronization frequency) The oscillator used for the carrier generation circuit and the oscillator for generating the pilot signal are also used. In addition, by configuring the circuit so that N is a multiple of 3, and by using both the frequency dividing circuit required for the carrier generation circuit and the frequency dividing circuit for the pilot signal generation circuit, the expensive X-tal element can be eliminated and the frequency dividing circuit can be Reduces chip area and power consumption by reducing the number of high-speed logic elements used in circuits.

FIG. 3 is a block diagram showing an embodiment of the present invention. The difference between FIG. 3 and FIG. 1 is that the frequency dividing circuit 18 of the phase locked circuit 24 in FIG.
It is divided into a frequency dividing circuit 50 and a second frequency dividing circuit 51, and the frequency division ratio of the first frequency dividing circuit 50 is 1/3, and the Xtal oscillator 25 in FIG. In FIG. 3, the output signal Si of the frequency dividing circuit 50 of FIG. 1 is connected to the frequency dividing circuits 26 to 29.

An embodiment of the present invention in a ±90 degree phase shift type NTC type recording circuit in the configuration shown in FIG. 3 will be described. The phase shift circuit 20 shifts the first field by +90 degrees every horizontal scanning period, and shifts the second field by -90 degrees every horizontal scanning period, thereby adjusting the color between the offset of ±1/ _4fH and the field. A signal frequency difference f _H /2 is generated. Therefore, the frequency of the output of the 1/8 frequency divider circuit 41 needs to be an integral multiple of _fH . If the output frequency of the 1/8 frequency divider circuit 41 is 45f _H , the oscillation frequency of the VCO 17 is f _VCO = 45f _H
×8= _360fH , and the frequency division ratio of the second frequency dividing circuit 51 is 3/360=1/120. On the other hand, the conditions for the pilot signal may be selected as f ₂ −f ₁ f ₄ −f ₃ f _H f ₃ −f ₁ f ₄ −f ₂ 3f _H as described above.

Therefore, the frequency division ratios 1/l ₁ , 1/l ₂ , 1/l ₃ and 1/l ₄ of the frequency dividing circuits 26 to 29 constituting the pilot signal generating circuit 40 may be selected as follows. In this case, l ₁ = 17 f ₁ 7.1f _H l ₂ = 15 f ₂ 8f _H l ₃ = 12 f ₃ 10f _H l ₄ = 11 f ₄ 10.9f _H , and f ₂ −f ₁ = 0.9f _H , f ₄ −f ₃ =0.9f _H f ₃ −f ₁ =2.9f _H and f ₄ −f ₂ =2.9f _H , so the conditions for the pilot signal are satisfied.

FIG. 4 is a diagram showing the tracks recorded on the tape and the position of the reproducing head. 4a to 4f indicate the tracks, 4g to 4k indicate the position of the reproducing head when tracking is deviated, and 4l indicates the running direction of the tape.

FIG. 5 is a diagram showing frequency characteristics of the first frequency discrimination circuit 34 and the second frequency discrimination circuit 35.

5a is the frequency, 5b is the output level, 5c is the first
5d is the band characteristic of the second frequency discrimination circuit 35, 5e and 5f are the frequencies of the output signal of the third converter 33,
5e corresponds to 0.9f _H and 5f corresponds to 2.9f _H.

FIG. 6 shows the track deviation amount and the output level of the frequency discrimination circuits 34 and 35 in the tracks 4b and 4d of CH-1. 6a is the amount of track deviation of the tape, and the positive direction corresponds to the case where the running speed of the tape is high. 6b shows the voltage, 6c shows the detection characteristics of the first frequency discrimination circuit 34, and 6d shows the detection characteristics of the second frequency discrimination circuit 35.

If the running speed of the tape increases with respect to track 4b in FIG. 4, the reproducing head will shift to position 4h, so the pilot signals to be reproduced are _f1 and _f2 .
Therefore, from the third converter 33 f ₂ −f ₁ =
The frequency of 8f _H −7.1f _H = 0.9f _H is output, and the result is shown in Figure 5, 5e.
As shown in FIG. 6C, an output signal is generated in the first frequency discrimination circuit 34 in accordance with the amount of track deviation.
On the other hand, if the running speed of the tape decreases, the reproducing head will shift to the 4g position, and the pilot signals to be reproduced will be _f1 and _f3 . Therefore, the third converter 33 outputs a frequency of f ₃ −f ₁ =10f _H −7.1f _H =2.9f _H according to the amount of track deviation as shown in FIG. 5f and 6d in FIG. Second frequency discrimination circuit 3
An output signal is generated at 5. FIG. 7 shows the amount of track deviation and the output level of the differential amplifier 36 for the tracks 4b and 4d of CH-1. 7a is the amount of track deviation, and is expressed as positive when the running speed of the tape is fast, and negative when it is slow. 7b is a voltage, and 7c is an amplification characteristic of the differential amplifier 36. Therefore, if the output of the differential amplifier 36 is positive, the running speed may be slowed down, and if it is negative, the running speed may be controlled to be fast.

If the running speed of the tape becomes faster with respect to track 4d, the reproducing head will shift to position 4j, and the pilot signals to be reproduced will be _f3 and _f4 . Therefore, from the third converter 33 f ₄ −f ₃ =10.9f _H −10f _H
= _0.9fH is output. On the other hand, if the running speed of the tape decreases, the reproducing head shifts to position 4i, so the pilot signals to be reproduced are _f2 and _f4 . Therefore, from the third converter 33, f ₄ −f ₂ =
10.9f _H −8f _H = 2.9f _H is output. In this case as well, the same control as that for the track 4b described above is possible.

FIG. 8 shows the amount of track deviation in tracks 4c and 4e of CH-2 and the frequency discrimination circuits 34 and 35.
output level. 8a indicates the amount of track deviation of the tape, 8b indicates the voltage, 8c indicates the detection characteristics of the first frequency discrimination circuit 34, and 8d indicates the detection characteristics of the second frequency discrimination circuit 35. With respect to track 4c in FIG. 4, if the running speed of the tape increases, the reproducing head will shift to position 4i, so the reproduced pilot signal will be f ₂
and _f4 . Therefore, the third converter 33
A frequency of f ₄ −f ₂ =10.9f _H −8f _H =2.9f _H is output from the track, and the output is sent to the second frequency discrimination circuit 35 according to the amount of track deviation as shown in FIG. 5, 5f, and FIG. 8, 8d. Occur. On the other hand, if the tape speed becomes slower, the playback head shifts to the 4h position, so the playback pilot signals are _f1 and _f2 . Therefore, a frequency of f 2 −f ₁ =8f _H −7.1f H =0.9f H is output from the third converter 33, and a frequency of f ₂ −f 1 =8f H −7.1f _H =0.9f _H is output as shown in FIG. An output is generated in the frequency discrimination circuit 34 of No. 1. Figure 9 shows track 4 of CH-2.
Track deviation amount and differential amplifier 3 for c, 4e
6 output level is shown. 9a is the amount of track deviation, and is expressed as positive when the running speed of the tape is fast, and negative when it is slow. 9b is a voltage, and 9c is an amplification characteristic of the differential amplifier 36. Therefore, the characteristic is opposite to that shown in FIG. 7 described above. In this case, by switching the changeover switch 38 in FIG. 3 to a position opposite to that shown in the figure, a signal with the characteristics inverted in FIG. 9 can be obtained, and similar control can be performed.

If the running speed of the tape becomes faster with respect to track 4e, the reproducing head shifts to position 4k, so the pilot signals reproduced are _f3 and _f1 . Therefore from the third converter 33 f ₃ −f ₁ =10f _H −7.1f _H
= _2.9fH is output. On the other hand, if the running speed of the tape decreases, the reproducing head shifts to position 4j, so the pilot signals to be reproduced are _f4 and _f3 . Therefore from the third converter 33 f ₄ −f ₃ =
10.9f _H −10f _H = 0.9f _H is output. In this case as well, the same control as that for the track 4c described above is possible.

The frequency dividing circuits 26 to 29 in FIG.
The frequency of Si is _120fH 1.9MHz, which is slower than conventional logic devices such as I ² L (Integrated
Injection Logic), the chip area and power consumption can be reduced when integrated into an IC. Moreover, since the expensive X-tal element required in the prior art is not required, an external circuit is also not required.

Next, in Figure 3, the ±45 degree phase shift method is shown.
An embodiment of the present invention in a PAL recording circuit will be described. The phase shift circuit 20 shifts the first field by +45 degrees every horizontal scanning period, and the second field by -45 degrees every horizontal scanning period, thereby adjusting the color signal frequency between the offset of ±1/ _8fH and the field. A difference f _H /4 is generated. Therefore, the frequency of the output of the 1/8 frequency divider circuit needs to be an integral multiple of _fH .
In this case, the oscillation frequency of VCO 17 is f _VCO is the same as the ±90 degree shift NTSC method mentioned above, and the pilot signal frequency is also the same, so if you want to realize the NTSC method and PAL method with a common IC, the phase shift is required. All that is required is to switch the circuit 20.

Next, in Figure 3, the +180 degree shift method is shown.
An embodiment of the present invention in an NTSC recording circuit will be described. The phase shift circuit 20 performs a +180 degree shift in the first field every horizontal scanning period, and does not perform a phase shift in the second field. This reduces the color signal frequency difference between the fields.
It is possible to generate f _H /2, but it is not possible to have a frequency offset of 1/4 f _H . Therefore, the input signal frequency of the phase shift circuit 20 is {n
±1/4(2k−1)}f _H (n, k; integer).

Now, if the frequency of the output of the 1/8 divider circuit 41 is (43-1/4) f _H , the oscillation frequency of the VCO 17 is f _VCO = 8 x (43-1/4) f _H = 342 f _H , The frequency division ratio of the second frequency dividing circuit 51 is 3/342.1/114. In this case, if the frequency dividing ratios of the frequency dividing circuits 26 to 29 are 1/17, 1/15, 1/12, and 1/11, respectively, the pilot frequency is f ₁
= 6.7f _H , f ₂ = 7.6f _H , f ₃ = 9.5f _H , f ₄ = 10.4f _H . The relationship between these frequencies is f ₂ − f ₁ = 0.9f _H f ₄ − f ₃ = 0.9f _H f ₃ − f ₁ = 2.8f _H f ₄ − f ₂ = 2.8f _H , which satisfies the pilot frequency condition. .

Next, we will discuss a PAC recording circuit that is compatible with the NTSC format. In order to set the color signal frequency difference between the fields to f _H /4, the phase shift circuit 20 shifts the first field by +90 degrees every horizontal scanning period, and does not shift the phase in the second field. In order to have a frequency offset of 1/ _8fH , the input signal frequency of the phase shift circuit 20 is set to {n±1/8(2k-1)} _fH .

Now, if the frequency of the output of the 1/8 frequency divider circuit 41 is (44-1/8) f _H , the oscillation frequency of the VCO 17 is f _VCO = 8 x (44-1/8) f _H = 351 f _H. The frequency division ratio of the frequency divider circuit 51 of 2 is 3/351=1/117. In this case, the frequency dividing ratios of the frequency dividing circuits 26 to 29 may be the same as those for NTSC, and if they are respectively 1/17, 1/15, 1/12, and 1/11, the pilot frequency is f ₁ = 6.9f. _H , f ₂ = 7.8f _H , f ₃ =
9.8f _H , f ₄ =10.6f _H. These frequency relationships are: f ₂ − _{f 1} = 0.9f _H , f ₄ − f ₃ = 0.9f _H f ₃ − f ₁ = 2.9f H , f ₄ − f ₂ = 2.8f _{H ,} which satisfy the pilot frequency conditions. be satisfied. Therefore, the above NTSC system and PAL system can be used as a common system.
If implemented using an IC, it is sufficient to switch between the phase shift circuit 20 and the second frequency divider circuit 51 as the IC.

In this case, the frequency of the signal Si input to the frequency dividing circuits 26 to 29 is 114f _H 1.8M in the case of the NTSC system.
Hz, in the case of PAL system, it is 117f _H 1.8MHz, so it can be realized with low-speed logic elements.

Next, an embodiment will be described in which the frequency of the output of the 1/8 frequency divider circuit 41 is set to (47 +1/4) f _H in a +180 degree shift type NTSC recording circuit. In this case, the oscillation frequency of VCO17 is f _VCO = 8 × (47 +
1/4) f _H =378f _H , and the frequency division ratio of the second frequency dividing circuit 51 becomes 3/378 = 1/126. Therefore, the frequency division ratios of frequency dividing circuits 26 to 29 are 1/18, 1/16, 1/13, and 1, respectively.
/12, the pilot frequencies are f ₁ = 7f _H , f ₂ = 7.9f _H , f ₃
=9.7f _H , f ₄ =10.5f _H . The relationship between these frequencies is f ₂ − f ₁ = 0.9f _H f ₄ − f ₃ = 0.8f _H f ₃ − f ₁ = 0.7f _H f ₄ − f ₂ = 2.6f _H , which satisfies the pilot frequency condition. .

Next, an embodiment will be described in which the frequency of the output of the 1/8 frequency divider circuit 41 is set to (46+1/8) _fH in a PAL system recording circuit using a -90 degree phase shift system that is compatible with the NTSC system. In this case, the oscillation frequency of the VCO 17 is _fVCO =8×(46+1/8)= _369fH , and the frequency division ratio of the second frequency dividing circuit is 3/369=1/123. Since the frequency division ratio of the frequency dividing circuits 26 to 29 is the same as that of the above-mentioned NTSC system, the pilot frequency is f ₁ =6.8f _H ,
f ₂ = 7.7f _H , f ₃ = 9.5f _H , f ₄ = 10.3f _H. The relationship between these frequencies is f ₂ − f ₁ = 0.9f _H f ₄ − f ₃ = 0.8f _H f ₃ − f ₁ = 2.7f _H f ₄ − f ₂ = 2.6f _H , which satisfies the pilot frequency condition. . In this case as well, in order to realize the NTSC system and the PAL system using a common IC, it is sufficient to switch between the phase shift circuit 20 and the second frequency dividing circuit 51 as the IC. In addition, in the case of the NTSC system, the frequency of the signal Si input to the frequency dividing circuits 26 to 29 is as follows.
126f _H 2.0MHz, 123f _H 1.9M for PAL system
Since it is Hz, it can be realized using low-speed logic elements.

The present invention is not limited to the embodiments described above, and is applicable to the oscillation frequency _Nf
and configure so that the above N is a multiple of 3,
For the oscillation frequency f of VCO _VCO , f ₁ = 1/3l ₁ f _VCO , f ₂ = 1/3l ₂ f _VCO , f ₃ = 1/3l ₃ f _VCO , f ₄ = 1/3l ₄ f _VCO You should choose one that satisfies you.

Also, regarding the configuration of the phase shift circuit 20,
It is not limited to the methods described in the above embodiments, for example, the NTSC method without phase shift, etc.
It goes without saying that the PAL system and its combination with this embodiment can be similarly implemented.

Furthermore, in this embodiment, 4 is used as the pilot signal.
Although we have described a method for recording signals of two different frequencies, it is obvious that the present invention can also be applied to, for example, a method of obtaining a pilot signal by shifting the phase of a signal of one frequency field by field. In the frequency dividing circuit 26-2
9. The frequency selection circuit 30 and tracking signal generation circuit 39 may be changed according to the pilot signal system.

According to the present invention, there is no need for an expensive X-tal element in the pilot signal generation circuit, and the chip area and power consumption can be significantly reduced when integrated into an IC. especially,
In the present invention, since the frequency of the pilot signal is exactly a multiple of the horizontal synchronization frequency, compatibility of recording tapes is excellent.

Furthermore, as described in the embodiments, the present invention can be implemented with various methods for offset between fields specific to color signals. of course
NTSC and PAL systems can be implemented using almost the same circuit, making them ideal for IC implementation.

[Brief explanation of drawings]

Figure 1 is a block diagram explaining the prior art, Figure 2 is a block diagram explaining the prior art.
3 is a block diagram illustrating an embodiment of the present invention, FIG. 4 is a diagram showing recorded tracks, and FIG. 5 is a diagram showing the output frequency of the converter in FIG. 3. , Fig. 6 is a characteristic diagram of the frequency discrimination circuit, Fig. 7 is a characteristic diagram of the differential amplifier, and Fig. 8 is a characteristic diagram of the frequency discrimination circuit.
The figure is a characteristic diagram of the frequency discrimination circuit, and FIG. 9 is a characteristic diagram of the differential amplifier circuit. 17; VCO, 50; first frequency divider circuit, 51;
Second frequency divider circuit, 26 to 29; Frequency divider circuit, 30;
Frequency selection circuit, 40; pilot signal generation circuit.

Claims (1)

[Claims] 1. A reference oscillator that oscillates at a specific oscillation frequency; A low-frequency conversion carrier generator that generates a low-frequency conversion carrier whose phase changes at a predetermined frequency from the oscillation signal from the reference oscillator; a mixer for generating a low-pass converted carrier color signal by mixing the low-pass converted carrier from the low-pass converted carrier generator and a carrier color signal to be recorded; A pilot generation circuit that generates a pilot signal with a frequency obtained by dividing the multiplied frequency; a synthesis circuit that synthesizes the low frequency conversion carrier color signal and the pilot signal; and an output signal from this synthesis circuit that is recorded on a magnetic tape. 1. A color signal recording device comprising: a magnetic head for detecting a color signal; 2. Mixing the carrier color signal to be recorded with a low frequency conversion carrier to convert the carrier color signal into a low frequency conversion carrier color signal, and when recording this converted low frequency conversion carrier color signal on a magnetic tape, A color signal recording method characterized in that a pilot signal having a frequency obtained by dividing a frequency obtained by multiplying the frequency of the low frequency converted carrier color signal by eight is generated and recorded together with the low frequency converted carrier color signal.