JPH0463645U - - Google Patents
Info
- Publication number
- JPH0463645U JPH0463645U JP10734190U JP10734190U JPH0463645U JP H0463645 U JPH0463645 U JP H0463645U JP 10734190 U JP10734190 U JP 10734190U JP 10734190 U JP10734190 U JP 10734190U JP H0463645 U JPH0463645 U JP H0463645U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply wiring
- ground line
- basic cells
- power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000015572 biosynthetic process Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Design And Manufacture Of Integrated Circuits (AREA)
Description
第１図は本考案の一実施例のレイアウト図、第
２図は、従来の半導体集積回路の一例を示すレイ
アウト図である。
１……基本セル、２ａ，２ｂ……電源配線、３
ａ，３ｂ……接地線、４ａ，４ｂ，４ｃ，４ｄ，
４ｅ，……電源配線、５ａ，５ｂ，５ｃ，５ｄ，
５ｅ……接地線、６……スルーホール、８ａ，８
ｂ……電源配線、９ａ，９ｂ……接地線。
FIG. 1 is a layout diagram of an embodiment of the present invention, and FIG. 2 is a layout diagram showing an example of a conventional semiconductor integrated circuit. 1... Basic cell, 2a, 2b... Power supply wiring, 3
a, 3b...ground wire, 4a, 4b, 4c, 4d,
4e, ... power supply wiring, 5a, 5b, 5c, 5d,
5e...Grounding wire, 6...Through hole, 8a, 8
b...Power supply wiring, 9a, 9b...Grounding wire.
Claims (1)
セル上に前記セル列に沿つて設けて前記基本セル
に電力を供給する第１の電源配線及び第１の接地
線と、前記第１の電源配線及び第１の接地線のそ
れぞれに接続して前記第１の電源配線及び第１の
接地線に電力を供給する第２の電源配線及び第２
の接地線を有する半導体集積回路において、前記
第２の電源配線及び第２の接地線が信号配線形成
領域の空き領域に分散して形成されたことを特徴
とする半導体集積回路。 a cell row in which basic cells are arranged side by side; a first power supply wiring and a first ground line that are provided on the basic cells along the cell row and supply power to the basic cells; and the first power supply wiring. and a second power supply wiring and a second power supply wiring connected to each of the first grounding wire and supplying power to the first power supply wiring and the first grounding wire.
1. A semiconductor integrated circuit having a ground line, wherein the second power supply wiring and the second ground line are formed in a distributed manner in an empty area of a signal wiring formation area.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10734190U JPH0463645U (en) | 1990-10-12 | 1990-10-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10734190U JPH0463645U (en) | 1990-10-12 | 1990-10-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0463645U true JPH0463645U (en) | 1992-05-29 |
Family
ID=31853810
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10734190U Pending JPH0463645U (en) | 1990-10-12 | 1990-10-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0463645U (en) |
-
1990
- 1990-10-12 JP JP10734190U patent/JPH0463645U/ja active Pending