JPH0464152A - Data write method - Google Patents

Abstract

PURPOSE:To read out at a high speed the data across multiple rows and columns in both the row direction and the column direction at the time of reading out the data, by providing the banks of 2N rows by 2N columns, and by writing successively the data of the M-th row, the number (2N+M)-th row and the (2X2N+M)-th row... in the bank of each column of the M-th row. CONSTITUTION:When N is defined as a positive integer, the banks of 2N rows by 2N columns are provided as a memory which stores the data across the multiple rows and columns. Then, when M is defined as a positive integer equal to or less than 2N, the data of the M-th row, the (2N+M)-th row, and the (2X2N+M)-th row... are successively written in the bank of each column of the M-th row. For example, when N equals 2, 2N equals 4, and M equals 1, the banks of 4 rows by 4 columns B11 - B14 are provided. Then, the data of the first row, the fifth row, and the ninth row... are written successively in banks B11 - B14 of each column of the first row, in the same state as the data of the first row and the first column is written in the bank B11 of the first row and the first column. Thus, the data across the multiple rows and columns is read out at high speed even when the data is read out in the column direction or the row direction at the time of reading out the data.

Description

Detailed Description of the Invention [Field of Industrial Application] This invention relates to a method for writing data spanning multiple rows and columns, such as image data for one field, into a memory for purposes such as analysis. .

``Prior art'' A subject image is captured by a video camera using a solid-state image sensor such as a CCD (1ft charge-coupled device), and the image signal for one field obtained from the video camera is converted into analog image data. After digitally converting the resulting image data and writing it to memory, the image data is read from memory and analyzed to check for local defects in the solid-state image sensor of the video camera. However, in order to write data that spans multiple rows and columns, such as image data for one field, to memory for purposes such as analysis, conventional memory for storing data is A method is used in which a plurality of banks are provided and sequentially obtained data is sequentially written into the plurality of banks.

FIG. 10 is an example of a data processing system that implements a conventional data writing method and an accompanying data reading method.
This is a case where four banks BO, Bl, B2 and B3 are provided.

The data to be written to banks BO to B3 are shown in the upper row of FIG. 11 as data Dll, D12. D13. DI4, D15...
・D21. D22. D23. D24°D25...D3
1. D32. D33. D34. D35...D41. D
42. D43. D44. D45...D51. D52.
D53. D54. D55...For example, it is an 8-bit data that spans many rows and columns as a whole, as shown below.
In the case of image data for one field, the column direction corresponds to the horizontal direction of the image, and the row direction corresponds to the vertical direction of the image. This data is given an X address (column address) and a Y address (row address) each expressed by 10 bits, for example. The 2 bits shown on the left in parentheses in the upper row of FIG. 11 are the lower 2 bits XI and Xo of the X address for that data, and the 2 bits shown on the right
The bits are the lower two bits yi and yo of the Y address for the data.

In the data processing system shown in FIG. 10, at the time of writing, the above 8-bit data is supplied to the data input terminal 1 and latched into the data launch circuit 2 by the clock CLK, and the above-mentioned total 20-bit X address and Y address are supplied to address input terminal 3 and latched by address latch circuit 4 by clock CLK.

Of the total 20 bits of the X address and Y address from the address latch circuit 4, the lower 2 bits Xi and XO of the X address are supplied to the decoder 5, and the lower 2 bits Xi and XO of the Accordingly, the clock CLK is sent to the four outputs of the decoder 5 as the latch clock LC.
The 8-bit data from the data latch circuit 2 is distributed and taken out as KO to LCK3, and is sent to the data latch circuit 60 by the latch clock LCKO, to the data latch circuit 61 by the rough clock LCKI, and to the data latch circuit 62 by the latch clock LCK2. , are latched by the data latch circuit 63 by the latch clock LCK3, and all of the upper 8 bits X9 to X2 of the X address and the Y address of the total 20 bits of the X address and Y address from the address latch circuit 4 are latched. 10 pins Y9 to YO are sent to the address latch circuit 70 by the latch clock and CKO, to the address latch circuit 71 by the latch clock LCKI, to the address latch circuit 72 by the latch clock LCK2, to the address latch circuit 73 by the rough clock LCK3,
latched data latch circuits 60, 61, 6, respectively.
2. The data from 63 are stored in banks BO, Bl, and Bl, respectively.
B2. Addresses ABO, ABI, AB2 . AB3 corresponds to banks BO, B1 . B2. It is supplied to address terminal A of B3. Note that the write control section is omitted in FIG. 10.

Therefore, as shown in the lower part of FIG. 11, the above data Dll, D12. D13. D14. D15...D2
1. D22. D23. D24. D25...D31
D32. D33. D34. D35...D41, D42
．． D43. D44. D45...D51°D52. D5
3. D54. D55... are sequentially written to banks BO to B3 according to their temporal order. That is, data Dll, D15...D21, D25...D3
1. D35...D41. D45...D51. D55
... is the lower 2 bits xt of the X address for this
, xo is OO, so it is written to bank BO, and data D12...D22...D32...D42
...D52... is the bank B1 because the lower two bits xi and xo of the X address for this are 01.
and data D13...D23...D33
...D43...D53... are written to bank B2 because the lower two bits XI and XO of the X address for this are 10, and data D14...D24
...D34...D44...D54... is the lower 2 pis of the X address for this +-X1, and the XO is 11
Therefore, it is written to bank B3.

When reading data written in banks BO to B3 over multiple rows and multiple columns in the column direction (X direction), the X address and Y address are supplied to the address input terminal 3 in the same way as when writing. , bank BO-B3 is accessed in the same way as when writing. Therefore, the above data Dll, DI2, D13 . D14. D15...D21
．． D22D23. D24. D25...D31. D32
．． D33, D34. D35...D41. D42. D4
3°D44. D45...D51. D52. D53. D
54, D55, . . . are sequentially read from banks BO-B3.

Then, the data from banks BO to B3 is supplied to the multiplexer 8, and the lower two bits XI and XO of the X address are transferred to the clock C in the cycle shift circuit 9.
LK shifts the data by a time corresponding to the access time of bank BO-83, and the shifted 2-bit data RXI - RXo is supplied to the multiplexer 8.
At multiplexer 8, data RX1. Data from bank BO, Bl, B2 or B3 is taken out as an output depending on the four contents of RXO.

Figure 12 shows the operation when reading in the column direction in this way, and as is clear from this, data spanning many rows and many columns can be read out in the column direction at high speed every cycle of the clock CLK. .

``Problems to be Solved by the Invention'' However, in the conventional data writing method described above, when reading data written in bank BO-83 spanning multiple rows and multiple columns in the row direction (Y direction),
For example, data D11, D21 . D31. D41
．． When reading D51... sequentially, the same bank must be accessed continuously by changing the Y address, such as changing the Y address sequentially and accessing the bank BO consecutively. There is a problem in that data cannot be read out at a high speed such as every cycle of the clock CLK due to the relationship with time.

Therefore, the present invention provides a method for writing data spanning multiple rows and multiple columns, such as image data for one field, into a memory for analysis, etc., when data spanning multiple rows and multiple columns is written. This allows high-speed reading in both the row and column directions.

"Means for solving the problem" In the invention of claim 1, when N is a positive integer,
As a memory for storing data spanning multiple rows and multiple columns, a bank of 2#I rows and 2H columns is provided, and when M is a positive integer less than or equal to 2N, the Mth row, (2N + M)th row, and the (2nd
x2N +M) rows... are sequentially written into the banks of each column of the Mth row.

In the invention of claim 2, when N is a positive integer,
As a memory for storing data spanning multiple rows and multiple columns, a bank of 2N rows and 2N columns is provided, and when M is a positive integer less than or equal to 2N, the Mth row, (2" + M)th row, and (2×
2N + M) rows... are sequentially written into the banks of each column of the M-th row, with the data of the M-th row and first column being written into the bank of the M-th row and M-th column.

As a specific example, N=2.2N-4, M=1.2°3.4
Then, a bank of 4 rows and 4 columns is provided, and the 1st row, 5th row,
The data in the 9th row... is the data in the 1st row and 1st column.
While writing to the bank in the first row and column, sequentially write to the banks in each column of the first row, the second row, the sixth row, the tenth row, etc.
The data in the 2nd row, 1st column is written to the bank in the 2nd row, 2nd column, and then the data is sequentially written in the banks in each column of the 2nd row, 3rd row, 7th row, 11th row, etc. The data of...
While writing the data in the 3rd row and 1st column to the banks in the 3rd row and 3rd column, sequentially write to the banks in each column of the 3rd row, and
The data in the rows, the 8th row, the 12th row, etc. are sequentially written into the banks in each column of the 4th row, with the data in the 4th row and 1st column being written in the banks in the 4th row and 4th column.

A bank of 2N rows and 2N columns means 2! This is a conceptual distinction between N banks, and does not necessarily mean that they must be arranged in 2N rows and 2N columns.

"Function" According to the data writing method of the invention of claim 1 or 2 which takes the above method, even when reading data spanning multiple rows and multiple columns in the column direction, when reading data in the row direction, However, since different banks need only be accessed sequentially, data can be read out at high speed.

Further, according to the data writing method of the invention of claim 2, in a data processing system for writing and successively writing data, the address latch circuit can be made common to banks in each row for each column, The circuit configuration of the data processing system is significantly simplified.

Embodiment FIG. 1 shows an example of a data processing system that implements the data writing method and associated data reading method of the present invention. This is a case where banks of 4 rows and 4 columns are provided up to bank B44.

The data written to banks B11-B44 is, for example, 8-bit data that spans many rows and many columns as a whole, as shown in the upper part of FIG. 2 in the same way as the upper part of FIG. 11. This data is given an X address (column address) and an X address (row address) each expressed by 10 bits, for example. The two bits shown on the left in parentheses in the upper row of FIG. 2 are the lower two bits Xi and XO of the X address for that data, and the two bits shown on the right are:
Lower 2 bits Yl, Y of the X address for that data
It is O.

In the data processing system shown in FIG. 1, at the time of writing, the above 8-bit data is supplied to the data input terminal 1 and latched into the data latch circuit 2 by the clock CLK, and the above-mentioned total 20-bit X address is and X
The address is supplied to address input terminal 3 and the clock C
It is latched by address latch circuit 4 by LK.

A total of 20 bits of the X address from the address latch circuit 4 and the lower 2 bits of the X address (XI, XO and the lower 2 bits of the X address) Yl, Y
O is supplied to the adder circuit 11, and from the adder circuit 11 the lower two bits XI, XO of the X address and the lower two bits Yl of the X address.

2-bit data A1 . . . whose contents change in four ways as shown in FIG. AO is obtained, the data Al and AO are supplied to the decoder 12, and as shown in FIG. The 8-bit data from the data latch circuit 2 is distributed and taken out as ~LCK3, and is sent to the data latch circuit 60 by the latch clock LCKO, to the data latch circuit 61 by the latch clock LCKI, and to the data latch circuit 62 by the rough clock LCK2. They are each latched by the data latch circuit 63 by the latch clock LCK3, and a total of 20 bits of the X address from the address latch circuit 4 and the upper 8 bits of the X address of the X address are
~X2 and the upper 8 bits Y9 to Y2 of the X address are
Address latch circuit 70 by latch clock LCKO
Then, it is latched by the address latch circuit 71 by the latch clock LCKI, by the address latch circuit 72 by the latch clock LCK2, and by the address latch circuit 73 by the latch clock LCK3.

Then, the data from the data latch circuit 60 is transferred to banks Bll, B21 . The data from the data latch circuit 61 is supplied to the data input terminals Di of the banks B31 and B41, and the data is supplied to the banks B12, B22 . B32 and B
The data from the data latch circuit 62 is supplied to the data input terminal Di of the third column bank B13. B23.
is supplied to the data input terminal DI of B33 and B43,
The data from the data latch circuit 63 is stored in bank B of the fourth column.
14. B24. Data input terminal D of B34 and B44
At the same time, the address ABO from the address latch circuit 70 is supplied to the banks B11.j of the first column. B21. B
31 and B41, and the address ABI from the address latch circuit 71 is supplied to the address terminal A of the second column bank 812B 22. The address AB2 from the address latch circuit 72 is supplied to the address terminals A of the banks B32 and B42, and the address AB2 from the address latch circuit 72 is applied to the third column bank B13. B23. The address AB3 from the address latch circuit 73 is supplied to the address terminals A of B33 and B43, and the address AB3 from the address latch circuit 73 is supplied to the bank B14 of the fourth column.
．． B24. It is supplied to address terminal A of B34 and B44.

Also, the lower two bits of Y address Y1. YO and the 2-bit data AI and AO from the adder circuit 11 are transferred to the bank Bll by the clock CLK in the cycle shift circuit 13.
- The data AI is shifted by a time corresponding to the access time of B44.

AO's shifted data WAI, WAO; 6
, write enable signal W according to the four types of WAO contents.
E sends the write enable signal W to the four outputs of the decoder 14.
The data is distributed and taken out as EO to WE3, and the lower two bits Yl and YO of the Y address are shifted data WY1. WYO is supplied to decoders 50-53,
Write enable signals WEO, WEI, WB2. WB2 is supplied to decoders 50, 51, 52, and 53, respectively, as shown in FIG. 6 (data WXI in the same figure).

WXO is the lower 2 bits of the X address, XI, assuming that XO is also shifted in the same way as the lower 2 bits of the Y address, Yl and YO.
, XO), the write enable signal WEO is output to the four outputs of the decoder 50 according to the four contents of the data WYI, WYO, respectively. WB21. WB21. W.B.
21 and the write enable signal WEI is sent to four outputs of the decoder 51 as write enable signals WE12 . WE22. WB32. The write enable signal WE2 is distributed and taken out as WB42, and the write enable signal WE13. W
B23. The write enable signal WE3 is distributed and taken out as WB23° to WB43, and the write enable signal WE3 is sent to the four outputs of the decoder 53 as the write enable signal WE14. WE24. WB3
4. It is distributed and taken out as WB44.

Then, the write enable signal WEI1. WEI2,W
B13. WB14 WB21. WB22°WB23.
WB24. WB31. WB32. WB23, WB24.
WB21. WB22. WB23° and WB44 are respectively banks Bll and B12. B13, B14. B21. B2
2. B23. B24°B31. B32. B33. B34
．． B41. B42, B43. It is supplied to the write enable terminal We of B44.

Therefore, the data D11 and B1 shown in the upper part of FIG.
5...B51. B55... is the lower two bits of the X address for this, X1. XO is 00, the lower two bits Yl and YO of the Y address are 00, and as shown in FIG. 5, data At and AO become OO, and the data D11. D1
5...B51. B55-- is the bank Bll in the first column
, B21. B31. At the same time, the bank Bll, B21, B31 or B41 is accessed, and as shown in FIG. 6, the write enable signal WEII is supplied to the bank Bll, thereby causing the is written to bank Bll in the first row and first column.

Similarly, for data D12...B52..., the lower two bits Xi and XO of the X address are 01, the lower two pins Yl and YO of the Y address are 00, and the data Al
, AO becomes 01, the data is written to bank B12 in the first row and second column, and the data D13...B53...
・is the lower 2 bits Xi, X of the X address for this
O is 10, lower 2 bits of Y address Yl, YO are 00
Then, when the data AI and AO become 10, the first
It is written to bank B13 in the third row and column, and data D14.
...B54... is the lower 2 of the X address for this
Bit X1, XO is 11, lower 2 bits of Y address Y
l.

When YO is 00 and data AI and AO are 11, data is written to bank B14 in the first row and fourth column, and data D21. For D25..., the lower two bits XI and XO of the X address are 0O1, and the lower two bits Yl and YO of the Y address are 01, and data Al and AO are 01, so that the bank in the second row and second column is Data D22... is written to B22, and the lower two bits Xi and XO of the X address are 01, the lower two bits Yl and YO of the Y address are 01, and the data Al and AO are 10. Data D23... is written to bank B23 in the second row and third column, and the lower two bits XI and XO of the X address are 10, and the lower two bits of the Y address are 10.
When bits Yl and YO are 01 and data Al and AO are 11, they are written to bank B24 in the second row and fourth column, and data D24... is written to the lower two bits XI and XO of the X address for this. is 11, the lower two bits of Y address Yl and YO are 01, and data Al and AO are 00
is written to bank B21 in the second row and first column, and the data D31. D35... is the lower 2 bits of the X address for this, XI, χ0 is 00, Y
The lower two bits Yl and YO of the address are 10, and the data A
'l, AO becomes 10, and data D32 is written to bank B33 in the third row and third column, and the lower two bits Xi, XO of the X address for this are 01.
, the lower two bins of the Y address) YI YO is 10, and data Al and AO are 11, so that the 4th bin of the 3rd row
The data D33 . XO is 10, lower 2 bits of Y address Yl, YO are 10,
When data At and AO become 00, they are written to bank B31 in the third row and first column, and data D34...
is the lower two bits xi, xo of the X address for this
is 11, and the lower two bits of Y address Y1. Since YO is 10 and data Al and AO are 01, data is written to bank B32 in the third row and second column, and data D41. D
45... corresponds to this, the lower 2 bits of the X address, X1°XO, are 00, and the lower 2 bits of the Y address, Yl, Y
Since O is 11 and data AI and AO are 11, it is written to bank B44 in the 4th row and 4th column, and data D42... is written to the lower 2 bits XI and XO of the X address as 01, Lower 2 bits of Y address Yl,
YO is 11, data AI.

When AO becomes OO, it is written to bank B41 in the 4th row and 1st column, and data D43... is written to the lower 2 bits Xi of the X address, XO is 10, and the lower 2 bins of the Y address) Yl , YO is 11, data AI
, AO becomes 01, data D44 is written to bank B42 in the 4th row and 2nd column, and the lower 2 bits Xi and XO of the X address for this become 11, Y
The lower two bits Yl and YO of the address are 11, and data A
l.

When AO becomes 10, it is written to bank B43 in the fourth row and third column.

That is, the data Dll, DI2 . D13, D
14. D15... is a state in which the data Dll of the first row and first column is written to the bank Bll of the first row and first column, and the banks Bll of the first row, B12°B13. B14, and the second row data D21. D22. D23. D
24. D25... is a state in which the data D21 in the second row and first column is written to the bank B22 in the second row and second column, and the data D21 in the second row and the second column are written in the bank B22. B23. B24. Data D31. D32. D33D3
4 D35... is a state in which the data D31 in the third row and first column is written to the bank B33 in the third row and third column, and the data D31 in the third row and third column are written in the bank B33. B34. B31°B32 are sequentially written, and the fourth row data D41°D42 D43.
D44. D45... is data D41 in the 4th row and 1st column.
is written to bank B44 in the fourth row and fourth column,
4th row bank B44°B41. B42. The data is sequentially written to B43, and data from the fifth row onward is written in the same way.

When reading data written in banks Bll to B44 over multiple rows and multiple columns in the column direction (X direction), the X address and Y address are supplied to the address input terminal 3 in the same way as when writing. , Bank Bll~B4
4 is accessed in the same way as when writing. Therefore, the third
As shown by the loop L1 in the figure, the first row of data D11. D
12°D13 D14 D15... is the first row of bank B11. B12. B13. B14. Bll..., and as shown in loop L2, the second row data D21. D22. D23. D24. D25... is the second row of bank B22. B23. B24. B21, B2
The third row of data D31 . D32. D33 D34. D
35... is the third row of banks B33°B34. B31.
B32. It is read out sequentially from B33..., and loop L4
As shown in the fourth row of data D41. D42. D43.
D44. D45... is the fourth row of bank B44. B41
．． B42. B43°B44... are read out sequentially,
The data on the fifth row and below are also read out in the same way.

Then, banks Bll, B21 . B31, B4
1 is fed to a multiplexer 80 and the data from the second
Column bank B12. 'B22. Data from banks B32, B42 are supplied to multiplexer 81, and data from banks B13 . B23. Data from banks B33, B43 are supplied to multiplexer 82, and data from banks B14 . B2
4. Data from B34 and B44 is sent to multiplexer 83
supplied to

Further, the lower two pins Yl and YO of the Y address and the 2-bit data AI and AO from the adder circuit 11 are transferred to the bank Bll by the clock CLK in the cycle shift circuit I5.
The data Al is shifted by a time corresponding to the access time of ~B44.

AO's shifted data RAI, RAO is decoder 1
6 and the data RAI, R as shown in FIG.
The multiplexer enable signal ME is distributed to the four outputs of the decoder 16 as multiplexer enable signals MEO to ME3 according to the four contents of AO, and then the shifted data of the lower two bits Yl and YO of the Y address are extracted. RYI and RYO are multiplexers 80
~83 and multiplexer enable signal ME
O, MEI, MB2. MB2 is multiplexer 80,8
1, 82, and 83, respectively, as shown in FIG.
, YO, assuming that it is shifted in the same way as YO.
In the multiplexer 80, during the high level period of the multiplexer enable signal MEO, the bank Bll of the first column is selected according to the four types of contents of the data RYI and RYO. , B21. Data from B31 or B41 is taken out as an output, and in the multiplexer 81, data is output from banks B12 . B22. Data from B32 or B42 is taken out as an output, and in the multiplexer 82, the third column banks B13, B23, . B33 or B
The data from the banks B14 . B24. Data from B34 or B44 is taken out as an output, and output data from multiplexers 80-83 is supplied to OR gate 17.

Figure 8 shows the operation when reading in the column direction in this way, and as is clear from this, data spanning many rows and many columns can be read out in the column direction at high speed every cycle of the clock CLK. .

When reading data written in banks Bll to B44 over multiple rows and multiple columns in the row direction (Y direction) as described above, the X address and Y address supplied to the address input terminal 3 are specified accordingly. be done. That is, the first column data Dll, D21 . D31. D41.
When sequentially reading D51..., the X address is the data DIlD21. D31 D41. D51... is fixed, and the Y address is for data Dll, D.
21°D31. D41. It is sequentially changed to those for D51... Therefore, at this time, as is clear from the upper part of FIG.
is always 00, and the lower two bits of the X address, Yl and YO, are 0.
It changes in the order of 0 01 10, 11.00..., and the second
As is clear from the lower part of the figure and Fig. 5, the data AI,
AO is 00. By changing in the order of 10°11.00..., the bank Bll in the first row and first column and the bank B in the second row and second column as shown by loop LLI in FIG.
22, the bank B33 in the third row and third column, the bank B44 in the fourth row and fourth column, the bank Bll in the first row and first column, etc. are sequentially accessed, and the banks Bll, B22. B33. B44
, Bll... to ]th column data Dll, D21, D
31. D41. D51... are sequentially read out.

Similarly, the X address supplied to the address input terminal 3 is the second column data D12. D22. D32°D42. D5
2..., and the X address is fixed to data D12. D22. D32. When sequentially changed to those for D42, D52, etc., the lower 2 of the X address
Bits XI and XO are always 01, and the lower two bits Yl and YO of the X address change in the order of 00°01.10, 11.00..., and data A, 1... AO is 01, 10.11.
By changing in the order of 00, 01, . . . , the bank BI2 . B23. B
54B41. B12... are sequentially accessed and banks B12, B23 . B34. B41. B12... to second column data DI2. D22. D32. D42゜D52
... are sequentially read out, and the X address supplied to the address input terminal 3 is the third column data D13°D23. D3
3. D43. Fixed to D53..., X
The address is data D13. D23°D33. D43. D
53. When changed sequentially to those for...
The lower two bits of the address, X1 and XO, are always 10, and the lower two bits of the X address, Yl and YO, are 00, 01, 10, 1.
It changes in the order of 1.00..., and the data AI and AO are 10.
．． By changing in the order of 11, 00, 01, 10, etc., bank B1 is changed as shown by loop L13 in FIG.
3°B24. B31. B42. B13... are sequentially accessed and the banks B13. B24. B31. B42゜B
13... to third column data DI3 D23 D
33, D43. D53... are read out sequentially, and the X address supplied to the address input terminal 3 is the fourth column data D14. D24. D34. D44 D54... is fixed, and the X address is fixed to data D14. D2
4. D34. D44. When sequentially changed to those for D54..., the lower two bits of the X address XI,
XO is always 11 and the lower 2 pis of Y address) Yl, YO
changes in the order of 00, 01, 10.11, 00...
Data A1. AO is 11.00, 01.10.11...
By changing in the order of ・, loop L14 in FIG.
As shown in bank BI4. B21. B32. B43°B14... are sequentially accessed and banks B14. B2
1, B32. B43. B14... and the fourth column data D14. D24. D34. D44. D54... are sequentially read out, and the data in the fifth column and below are read out in the same way.

Figure 9 shows the operation when reading out in the row direction in this way, and as is clear from this, data spanning many rows and columns can be read out in the row direction at high speed every cycle of the clock CLK. .

"Effects of the Invention" As described above, according to the data writing method of the invention of claim 1 or 2, data spanning multiple rows and columns can be read at high speed in both the row and column directions when data is continuously written. I can do it. Furthermore, according to the data writing method of the invention as claimed in claim 2, the address latch circuit can be made common to banks in each row for each column in the data processing system as shown in the illustrated example, and the data processing system The circuit configuration becomes significantly simpler.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of a data processing system that implements the data writing method and associated data reading method of the present invention, and FIG. FIG. 3 is a diagram illustrating the access order of banks when data written in a bank of 4 rows and 4 columns spanning multiple rows and columns is read in the column direction. FIG. 4 is a diagram showing the access order of banks when data written in the 4 rows and 4 columns of banks over multiple rows and multiple columns is read in the row direction, and FIGS. 5, 6, and 7 are , a diagram for explaining the operation of the data processing system shown in FIG. 1, respectively;
FIG. 8 is a time chart for explaining the operation when data spanning multiple rows and columns is read out at high speed in the column direction in the data processing system of FIG.
A time chart for explaining the operation when reading data spanning multiple rows and columns at high speed in the row direction in the data processing system shown in the figure. Figure 10 shows a conventional data writing method and an associated data reading method. FIG. 11 is a block diagram showing an example of a data processing system that processes data. FIG. 2 is a time chart illustrating an operation when data written across multiple rows and columns is read out at high speed in the column direction. FIG.

Claims (2)

[Claims] (1) When N is a positive integer, a bank of 2^N rows and 2^N columns is provided as a memory for storing data spanning multiple rows and multiple columns, and M is a positive integer less than or equal to 2^N. When, Mth row, (2nd
A data writing method in which data in the ＾N+M) row, (2×2＾N+M)th row, etc. is sequentially written to the bank in each column of the Mth row. (2) When N is a positive integer, a bank of 2^N rows and 2^N columns is provided as a memory for storing data spanning multiple rows and multiple columns, and M is a positive integer less than or equal to 2^N. When, Mth row, (2nd
^N+M) rows, (2×2^N+M) rows, etc., with data in the Mth row and 1st column being written to the banks in the Mth row and Mth column. A data write method in which data is written sequentially to banks of columns.