JPH0464182B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Technical Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an isolation region between elements.

(b) Prior Art and Problems Conventionally, isolation regions between elements in relatively highly integrated semiconductor ICs have been often formed by selective oxidation technology (LOCOS method) or U-groove isolation technology.

Selective oxidation technology selectively thermally oxidizes the semiconductor substrate surface using an oxidation-resistant film patterned to a predetermined size corresponding to the element formation area as a mask, and separates and defines the element formation area on the semiconductor substrate surface. This is a technology to form an isolation oxide film.

However, in this technology, as shown in Fig. 1, a bird's beak BB with a width w comparable to the thickness t of the selective oxide film OX extends below the oxidation-resistant film SiN, so that the isolation region is There is a problem that the width of the bird's beak becomes wider (the minimum isolation region width is currently about 2.2 [μm]), which impedes higher density of the IC, and the width of the bird's beak varies depending on the manufacturing conditions. It is difficult to keep the area of the element formation region defined by There was a problem in that device performance deteriorated due to variations in capacitance due to changes in area.

U-groove isolation technology involves forming a U-shaped isolation groove on the surface of a semiconductor substrate using anisotropic etching technology, and depositing an insulating layer on the substrate having the U-shaped isolation groove with a thickness sufficient to fill the groove. , or a U in which an insulator or polycrystalline silicon is flatly embedded by forming a high resistivity polycrystalline silicon layer and uniformly etching and removing the insulator layer or polycrystalline silicon layer from the top surface.
This is a technique in which a U-shaped separation groove is formed and an element formation region is separated and defined by the U-shaped separation groove.

However, the U-groove isolation technique has the problem that the method of planar etching the insulator layer or polycrystalline silicon layer is extremely complicated and unfavorable in terms of the manufacturing process. is formed by a plasma sputtering method with good coverage, so the impact of the plasma can cause problems in the crystal quality, which can cause deterioration in device performance, such as an increase in leakage current on the surface of the device formation area and a decrease in carrier energy lifetime. There were problems such as a decrease in the amount of water.

(c) Purpose of the Invention The purpose of the present invention is to provide a method for forming an isolation region between elements whose dimensions can be defined finely and accurately using lithography technology, and which does not impair the crystal quality of a semiconductor substrate. The goal is to increase the density and integration of semiconductor ICs and improve their quality.

(d) Structure of the Invention In other words, the present invention is a method for manufacturing a semiconductor device, in which an insulating film is formed on the semiconductor substrate, and an insulating film is formed by penetrating the insulating film when forming an element isolation region on the surface of the semiconductor substrate. A U-shaped groove is formed in the semiconductor substrate, and the U-shaped groove is formed in the semiconductor substrate.
Selectively implant impurity ions into the inner surface of the shaped groove,
selectively growing a semiconductor layer epitaxially in a non-doped manner on the inner surface of the U-shaped groove; simultaneously diffusing the implanted impurity into the semiconductor epitaxial layer; and oxidizing the surface of the semiconductor epitaxial layer. Features.

(e) Embodiments of the Invention The present invention will be described in detail below with reference to the drawings.

2A to 2F and 3A to 3H are process sectional views of a different embodiment, and FIGS. 4A to 4D are process sectional views of a modified example.

Refer to Figure 2 A. When forming, for example, a MOSIC using the method of the present invention, for example, a p ^- type silicon (Si) substrate 1
A silicon dioxide (SiO 2 ) film 2 with a thickness of about 2000 [Å] is formed on the surface of the substrate by a normal thermal oxidation method, and then a silicon dioxide (SiO ₂ ) film 2 with a width of about 1 [μm], for example, is formed on the substrate to define an element isolation region Iso width. A resist film 4 having openings 3 of W _I is formed, and then, using the resist film 4 as a mask, SiO ₂ is etched using an anisotropic etching method that is predominant in the direction perpendicular to the substrate surface, such as a reactive ion etching method. A U-shaped groove 5 having a depth d of, for example, about 1 [μm] is formed on the surface of the Si substrate by penetrating the film 2 . Note that the etching gas used in the above reactive ion etching method is the same as usual.
For SiO ₂ , use methane trifluoride (CHF ₃ ), etc.
For Si, carbon tetrafluoride (CF ₄ ) or the like is used.

Refer to FIG. 2B Next, the remaining film of the resist film 4 and the SiO ₂ film 2
Using as a mask, a p-type impurity, ie, boron (B ⁺ ), is applied to the inner surface (particularly the bottom surface) of the UZ-shaped groove 5 at a dose of 3×10 ¹⁵ [atm/cm ² ] and an acceleration energy of about 70 to 100 [Kev]. Selectively implant ions at high concentration.
6 indicates the B ⁺ injection region.

Refer to Figure 2 C. After removing the resist film 4, the temperature is 1050 [℃]
A second SiO ₂ film 7 with a thickness of about 2000 [Å] is formed on the inner surface of the U _- shaped groove 5 by thermal oxidation treatment at a temperature of about The entire surface is etched using the wet etching method until the SiO ₂ film on the inner surface of the U-shaped groove 5 is removed. At this time, the thickness of the SiO ₂ film 2 on the upper surface of the substrate 1 returns to almost the original thickness. This process is carried out as a precaution in order to remove crystal defects formed on the inner surface of the U-shaped groove 5 during the reactive ion etching and ion implantation, and to increase the surface concentration of B ⁺ on the inner surface of the U-shaped groove 5. It is added, and can usually be omitted.

This is because the crystal defects are sufficiently removed in the next epitaxial growth step, and even without increasing the B ⁺ surface concentration on the inner surface of the U-shaped groove 5, autodoping of B ⁺ into the epitaxial layer, which will be described later, is possible. Because it is fully done.

See Figure 2 D. Next, add trichlorosilane (SiHCl ₃ ) to the reaction gas.
in the reaction gas of about 0.1 [Torr].
By using the usual selective epitaxial growth technique for Si, which is carried out at a temperature of about 1000 [°C], the inner surface of the U-shaped groove 5 where Si is exposed is selectively grown to a thickness of, for example, 3000°C.
Grow non-doped Si of about [Å]. At this time, the above-mentioned
B ⁺ is diffused (autodoped) into the Si epitaxial layer from the B ⁺ implanted region 6, and the Si epitaxial layer becomes a p ⁺ type Si epitaxial layer 8. Note that the epitaxial layer 8 may be formed to a thickness that fills the U-shaped groove 5 almost to the top surface.

Refer to FIG. 2 E. Next, the surface of the ^p
A third SiO ₂ film 9 having a thickness of approximately [Å] is formed to complete the element isolation region Iso according to the present invention. At this time, the SiO ₂ film 2 on the element formation area Dev has a density of 3000~
It becomes thick to about 4000 [Å].

Refer to FIG. 2 Next, after selectively removing SiO ₂ 2 on the element formation region Dev, a new gate oxide film 10 is formed on the element formation region Dev according to a normal MOS transistor formation method. A polycrystalline silicon layer is formed on the substrate and patterned to form a polycrystalline silicon gate electrode 11. Then, using the gate electrode 11 as a mask, selective ion implantation of n-type impurities is performed to form an n ⁺ type source. , drain region 12a,
12b is formed.

Then, the MOSIC is completed by forming an insulating film (not shown), forming electrode contact windows, forming wiring, etc.

Refer to FIG. 3A. When forming, for example, a bipolar IC using the method of the present invention, an n ⁺ -type buried diffusion region 13 is formed on one surface of a p ^- type Si substrate, for example, and N ^- type with a thickness of about 1.5 [μm]
A SiO 2 film 2 having a thickness of, for example, about 2000 Å is formed by a normal thermal oxidation method on a substrate to be processed for forming a bipolar IC on which a Si epitaxial layer 14 is formed, and then a SiO _{2 film 2} with a thickness of about 2000 Å is formed on the SiO ₂ film 2. A resist film 4 having apertures 3 with a width corresponding to the element isolation region Iso width is formed on the surface, and using the resist film 4 as a mask, a reactive ion etching method similar to the above embodiment is performed.
The bottom is p ^- type through the SiO ₂ film 2 and onto the surface of the substrate to be processed.
A U-shaped groove 5 reaching into the Si substrate 1 is formed.

Refer to FIG.
Using the SiO ₂ film 2 as a mask, B ⁺ ions are implanted.
High concentration is selectively applied to the inner surface, especially the bottom surface, of the U-shaped groove 5.
A B ⁺ implantation region 6 is formed.

Refer to FIG. 3C. Next, after removing the resist film 4, a Si epitaxial layer is selectively grown in the U-shaped groove 5 by using the same selective epitaxial growth technique as in the previous embodiment to fill the U-shaped groove 5 almost to the top surface. let At this time, as mentioned above, the high concentration B ⁺ is added to the epitaxial layer.
Autodoping of B ⁺ is performed from the implantation region 6,
This layer becomes a p ⁺ type Si epitaxial layer 8. Applicable
Before the selective epitaxial growth of Si, a step of removing crystal defects on the inner surface of the U-shaped groove as described in the above embodiment may be added.

Refer to Fig. 3 D. Next, the inside of the U-shaped groove 5 is formed by a normal thermal oxidation method.
For example, 2000 μm is applied to the surface of the p ⁺ type Si epitaxial layer 8.
A third SiO ₂ film 9 having a thickness of about [Å] is formed, and the inter-element isolation region Iso is completed. The separation in this case is mainly junction separation.

Refer to FIG. 3E Next, a p-type base region 15, an n ⁺ -type emitter region 16, and an n ⁺ -type collector contact region 17 are formed in the element formation region Dev according to a normal bipolar transistor formation method using ion implantation technology. will be done.

Although not shown, wiring, insulating films, etc. are then formed to complete the bipolar IC.

In all of the above examples, a SiO ₂ film was used as a protective film on the substrate surface when forming a U-shaped separation groove, but a silicon nitride (Si ₃ N ₄ ) film was used as the protective film. Sometimes.

This is done by forming a particularly thick SiO ₂ film on the isolation region between the elements, and removing the wiring passing over the isolation region and the SiO2 film in the isolation trench.
It can improve the insulation with the epitaxial layer, reduce the stray capacitance of wiring, and
When a junction isolation structure is used as in an IC, it is advantageous to reduce isolation capacitance. A method for forming an isolation region between elements when a Si ₃ N ₄ film is used as the surface protection film will be explained with reference to FIG.

Refer to Figure 4 A. For example, on a p ^- type Si substrate 1, by the usual thermal oxidation method,
An initial oxide film 18 of about 500 to 1000 [Å] is formed,
A Si ₃ N ₄ film 19 with a thickness of about 1000 [Å] is formed on the initial oxide film 18 by ordinary chemical vapor deposition.
A resist film 4 having openings 3 having a width corresponding to the width of the inter-element isolation region Iso is formed on the Si ₃ N ₄ film 19 using a normal photo process, and the Si ₃ N ₄ film 19 is removed using a reactive ion etching method. Then, a U-shaped groove 5 is formed on the substrate surface through the initial oxide film 18.

Refer to FIG. 4B Next, the remaining film of the resist film 4 and the Si ₃ N ₄ film 1
9 Using the initial oxide film 18 as a mask, ion implantation is performed to selectively implant B ⁺ ions into the inner surface (particularly the bottom surface) of the U-shaped groove 5 at a high concentration. 6 indicates the B ⁺ injection region.

Refer to FIG. 4C. After removing the resist film 4, a Si epitaxial layer is selectively grown in the U-shaped groove 5, and the U-shaped groove 5 is grown selectively.
A p ⁺ type Si epitaxial layer 8 is formed within the shaped groove 5 . (As mentioned above, it becomes p ⁺ type due to autodoping from the B ⁺ implanted region 6.) See Figure 4 d. Next, using the Si ₃ N ₄ film 19 as a mask, p ⁺ type Si epitaxial is formed by the usual selective oxidation method. A third layer having a thickness of, for example, about 3000 [Å] is selectively formed on the upper surface of layer 8.
The SiO ₂ film 9 of the present invention is formed to form an element isolation region of the present invention
Iso is completed. Note that during the selective oxidation, the third
A bird's beak extends from the SiO ₂ film 9, but the third
Since the thickness of the SiO ₂ film 9 is thinner than that of the conventional oxide film isolation structure (see FIG. 1), the extension width of the bird's beak is minute.

Thereafter, after removing the Si ₃ N ₄ film 19 and the initial oxide film 18 on the element formation region Dev, a semiconductor element is formed in this region by a normal method.

(f) Effects of the Invention As is clear from the above embodiments, according to the method of the present invention, the width of the isolation region between elements is determined by the photolithography technique when forming the U-shaped isolation groove. Therefore, a micro-width inter-element isolation region having the limit width that can be patterned in photolithography technology (currently about 1 [μm]) can be formed without variation as the patterning accuracy of photolithography technology increases. Accordingly, variations in the area of the element forming region are also extremely reduced.

Therefore, according to the present invention, it becomes possible to further increase the density and integration of semiconductor ICs, and improve the quality thereof.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of an element isolation technique using a conventional selective oxidation method, and FIGS. In the drawings, FIGS. 4A to 4D are process sectional views of a modification thereof. In the figure, 1 is a p ^- type silicon substrate, 2 and 9 are silicon dioxide films, 3 is an opening, 4 is a resist film,
5 is a U-shaped trench, 6 is a boron implanted region, 8 is a p ⁺ type silicon epitaxial layer, 18 is an initial oxide film,
19 is a silicon nitride film, Iso is an isolation region between elements,
Dev indicates the element formation area.

Claims (1)

[Claims] 1. When forming an element isolation region on a semiconductor substrate surface, an insulating film is formed on the semiconductor substrate, and a U-shaped groove is formed in the semiconductor substrate through the insulating film,
selectively implanting impurity ions into the inner surface of the U-shaped groove, selectively growing a non-doped semiconductor layer epitaxially on the inner surface of the U-shaped groove, and simultaneously diffusing the implanted impurity into the semiconductor epitaxial layer; A method for manufacturing a semiconductor device, comprising the step of oxidizing the surface of the semiconductor epitaxial layer.