JPH0464213B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of an intermediate frequency amplifier of a receiver, and particularly relates to a method of detecting a received electric field of a receiver. , Microelectronics and Reliability;
No. 16, pp. 345-366, Pergamon Press
Published in 1977 (Microelectronics and Reliability,
vol.16, pp, 345-366. Pergamon Press, 1977)
exists. The circuit configuration shown in FIG. 3, which is disclosed as a conventional example of the present invention, is shown in the above-mentioned document.
This is an extracted part of the IC called CA3089.
Other parts in the above document that are related to Figure 3 of this specification are Figure 1, Figure 2, Figure 10, Figure 11, and Figure 12.
and its explanatory text.

Conventionally, the configuration of an intermediate frequency amplifier having an electric field detection function is as shown in FIG.
2nd stage consisting of 1' to Q19';Q20' to Q2
The output of each stage (third stage consisting of 7') was rectified via capacitors (C8, C9, C10), and the rectified current waveforms of each stage were added to produce electric field level information.

Problems to be Solved by the Invention The above-mentioned conventional intermediate frequency amplifier having an electric field detection function uses a diode (Q28',
Q29', Q30';Q32',Q33', Q3
4';Q35',Q36',Q37'), the disadvantage is that the temperature characteristics are particularly poor and the circuit becomes complicated to compensate for the temperature characteristics.

Further, since the rectifier is a half-wave rectification method using diodes as described above, a capacitor (C8, C9, C10) is required for each rectifier, and if the intermediate frequency is lowered, a larger capacitor is required.
Therefore, when the above-mentioned capacitor is built into an IC, the chip size becomes large. Furthermore, in order to reduce the chip size by attaching an external capacitor, an external capacitor is required for each stage, which increases the number of terminals for external capacitors, which is disadvantageous for IC implementation. Furthermore, the rectifier uses diodes as mentioned above, and can only detect signal input up to the point where the first stage differential amplifier consisting of transistors Q1' to Q10' is saturated, which limits the dynamic range. Even if the total gain of the differential amplifier was increased by increasing the total gain of the differential amplifier, the maximum input level was determined at the above-mentioned saturation level, and a sufficient dynamic range could not be obtained. On the other hand, in order to reduce the deviation of the input signal detection voltage from the logarithmic characteristic, it is generally necessary to lower the gain per stage of the differential amplifier mentioned above and increase the number of stages, and the number of capacitors required is equal to the number of stages of the rectifier. There were flaws.

The present invention has been made in view of the above-mentioned conventional circumstances, and therefore, an object of the present invention is to eliminate the above-mentioned disadvantages inherent in the conventional technology.

Means for Solving the Problems In order to achieve the above object, the intermediate frequency amplifier circuit with electric field strength detection function according to the present invention uses a double-wave rectifier consisting of a differential amplifier and a double-balanced differential amplifier. It is an intermediate frequency amplifier circuit obtained by connecting multiple stages in cascade, and the differential amplifiers constituting the double-balanced differential amplifier in each stage consist of two differential amplifiers connected in parallel with each other, each having a different gain. are doing.

Embodiment Next, a preferred embodiment of the present invention will be specifically described with reference to the drawings.

FIG. 1 is a circuit configuration diagram illustrating a four-stage configuration as an example of an embodiment of the present invention.

Transistors Q1 to Q10 constitute a first stage double wave rectifier, transistors Q11 to Q20 constitute a second stage double wave rectifier, and transistor Q2
Transistors 1 to Q3B constitute a third-stage double-wave rectifier, and transistors Q31 to Q40 constitute a fourth-stage double-wave rectifier.

The adder circuit ADD adds the positive-phase output currents from the first-stage double-wave rectifier to the fourth-stage double-wave rectifier, smoothes this added current with resistor R17 and capacitor C1, and adjusts the input signal level. DC voltage
Output in Vs.

Now, as the IF input signal V _IN gradually increases, it begins to saturate from the double balanced differential amplifier in the succeeding stage. Here, R3=R4=R7=R8=R11=R12=
If R15=R16=RE, the small signal gain of the two parallel-connected differential amplifiers constituting each double-balanced differential amplifier can be expressed as follows.

However, V _T =k _T /q...(1) where k: Boltzmann's constant T: absolute temperature q: unit electronic charge Regarding the first stage double-balanced differential amplifier,
Gain g ₁₁ of differential amplifier with current source I2'
is g ₁₁ = I2′/2V _T ……(2) Gain g ₁₂ of differential amplifier with current source I3
is g ₁₂ = I3/(2V _T + REI3) ...(3).

Regarding the second stage double balanced differential amplifier,
The gain g ₂₁ of the differential amplifier with current source I ₂ is g ₂₁ = I2 / 2V _T ... (4) The gain g ₂₂ of the differential amplifier with current source I 3
is g ₂₂ = I3/(2V _T + REI3) ...(5).

Regarding the third stage double balanced differential amplifier,
The gain g ₃₁ of the differential amplifier with current source I2 is g ₃₁ = I2/2V _T ...(6) The gain g ₃₂ of the differential amplifier with current source I3 is
is g ₃₂ = I3/(2V _T + REI3) ...(7).

Regarding the fourth stage double balanced differential amplifier,
The gain g ₄₁ of the differential amplifier with current source I2 is g ₄₁ = I2/2V _T ……(8) The gain g ₄₂ of the differential amplifier with current source I3′ is
can be expressed as g ₄₂ = I3′/(2V _T + REI3′) ……(9).

Here, if I2 = I2' = I3 = I3', then g ₁₁ = g ₂₁ = g ₃₁ = g ₄₁ ... (10) g ₁₂ = g ₂₂ = g ₃₂ = g ₄₂ ... (11). Now, assume that the gains of all the differential amplifiers from the first stage to the fourth stage are g ₀ .

Using equations (10) and (11), the emitter resistance RE can be set so that g ₁₁ =√ ₀・g ₁₂ ...(12). In this case, the average output sink current Is in Figure 1
The characteristic of is a curve as shown by Is in Figure 2, and V _IN
It can be seen that the relationship between (dB) and rectified output current characteristics is almost linear. However, G ₀ (dB) = 20log g ₀ ... (13) This will be explained in detail below.

The curve 1 in Fig. 2 is the circuit diagram of Fig. 1, and the transistors Q7, Q8; Q17, Q18; Q27, Q2
8; This is the characteristic when the four differential amplifiers composed of Q37 and Q38 are removed, and is composed only of the differential amplifier with the gain shown by equation (11).

The two curves in Figure 2 are for transistors Q9, Q10, Q19, Q20, Q29, Q3 in the circuit diagram in Figure 1.
This is the characteristic when the four differential amplifiers composed of 0, Q39, and Q40 are removed, and is composed only of the differential amplifier with the gain shown by equation (10).

Here, as can be seen from equation (12), curve 2 is curve 1
The size of the emitter resistor RE is selected so that the sensitivity of the rectifier is lower by G ₀ /2 dB than in the case of .

Incidentally, V _IN (dB) in FIG. 2 has Is characteristics, etc., which will hereinafter be referred to as a log characteristic curve.

Curves 1 and 2 in FIG. 2 are four curves each undulating in a concave and convex manner, and the logarithmic characteristic is approximated. In this way, generally when a logarithmic characteristic curve is approximated by a polygonal line using a linear amplifier, a deviation from the logarithmic characteristic always occurs as shown in curves 1 and 2 in FIG. It is well known that there is no other way to reduce this deviation from the logarithmic characteristic than by increasing the number of stages of the polygonal line approximation.

However, in the circuit diagram of FIG. 1, the differential transistor pairs constituting the double balanced operational amplifier in each stage, namely transistors Q7 and Q8 and transistors Q9 and Q10;
and transistors Q19, Q20; transistor Q
27, Q28 and transistors Q29, Q30; transistors Q37, Q38 and transistor Q3
9 and Q40 have the same phase, so the characteristics of the output sink current Is of the field strength detection function shown in the circuit diagram of Figure 1 are the sum of curves 1 and 2 shown in Figure 2. . Here, the emitter _resistor RE
It can be seen that by selecting , the undulating unevenness cancels out each other and improves the linearity.

Effects of the Invention As explained above, according to the present invention, in an intermediate frequency amplifier circuit obtained by cascading a differential amplifier and a double balanced differential amplifier in multiple stages, two wave rectifiers constitute a double-wave rectifier in each stage. By connecting two double balanced differential amplifiers having different gains in parallel, it is possible to improve the linearity of the log characteristic of the DC output with respect to the input voltage.

In this circuit configuration, since the positive-phase output current waveforms of the double-balanced differential amplifiers are in phase, addition is possible without converting to direct current using a capacitor.

According to the present invention, a 2n-stage differential amplifier and
Log characteristics with linearity equivalent to that of an intermediate frequency amplifier with an electric field detection function consisting of a 2n-stage rectifier can be obtained. Furthermore, the differential pair configuration also improves temperature characteristics.

As described above, according to the present invention, an intermediate device having an electric field detection function that operates from a low intermediate frequency, has excellent temperature characteristics of the electrolytic detection voltage, has a wide dynamic range with a high saturation input signal level, and has significantly improved linearity. The frequency amplification circuit can be realized with a relatively small circuit scale, and the capacitor can be omitted, which is a great advantage.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram of an embodiment of the present invention configured in four stages. FIG. 2 shows the characteristics of the sink current Is of the DC voltage output in the circuit diagram of FIG. 1, and the curve 1 in FIG. 2 shows the transistors Q7, Q8; Q17, Q18;
Q27, Q28: Characteristics when Q37, Q38 are removed, curve 2 is for transistors Q9, Q
10;Q19,Q20;Q29,Q30;Q3
9, Q40 and resistors R3, R4; R7, R8; R11,
R12: This is the characteristic when R15 and R16 are removed.
FIG. 3 shows an example of a conventional circuit consisting of a three-stage differential amplifier circuit. FIG. 4 shows the output voltage of S-METER OUT in FIG. 3 with respect to the signal level V _IN (dB) of the IF input. Q1-Q40...Transistor, R1-R17...Resistor, C1...Capacitor, I1, I2, I2', I3, I3'...
...constant current source, V _IN ...IF input signal, V0 ...IF output signal, Is ...output sink current, ADD ...addition circuit.

Claims (1)

[Claims] 1. There are n stages of differential amplifiers, and an intermediate frequency amplifier is configured in which the output of each differential amplifier is sequentially connected to the input of the next stage, and the output signal of each stage of the differential amplifier is connected to the first stage. There are n double-balanced differential amplifiers corresponding to the differential amplifiers whose second inputs are the input signals in each stage of the differential amplifier, and the n double-balanced differential In an intermediate frequency amplifier configured with a circuit that adds the positive-sequence output currents of the amplifiers, the differential amplifier to which the second input of the double-balanced differential amplifier is applied has a circuit that adds the positive-sequence output currents of the respective amplifiers. Intermediate frequency with electric field strength detection function characterized by a differential pair in which emitters are commonly connected and a differential pair in which emitters are commonly connected without an emitter resistor being connected in parallel to each other. Amplification circuit.